The SPIL silicon compiler accepts an algorithmic description of a digital system in a Pascal-like language and generates CIF layouts using a register-transfer architecture, having a data path controlled by a finite state machine (FSM). For SPIL to be effective, its output is analysed by a performance evaluator, EPAD. EPAD estimates propagation delays, power dissipation and silicon area of CMOS circuits. Performance estimates can be used iteratively to modify the SPIL input and its intermediate compilation steps. Two design examples were generated, a codec chip for encoding and decoding pulse code to/from adaptive delta modulation signals, and a chip for controlling the timing and exponent calculation for floating-point addition and subtration. Both examples have been fabricated using a 3 micrometre CMOS technology. Test results show the effectiveness of SPIL and EPAD.