Citation

Brent R. Petersen, "A digital fault simulator implemented in SPLICE," B.Eng. project report, Department of Electronics, Carleton University, Ottawa, Ontario, Canada, April 12, 1985.

Abstract

Due to the complexity of integrated circuits, the process of testing a manufactured integrated circuit has become a difficult problem. Such a problem can only be solved by a methodical approach to the testing process. A software tool called a fault simulator helps to meet this requirement.

A fault simulator is a particular feature of an integrated-circuit simulation program. The purpose of a fault simulator is to determine how how a circuit's input signals exercise all of the functions of the circuit. The fault simulator tests the circuit's input signals and not the circuit. The set of input signals which drive the circuit is known as the test pattern.

A critical part of the fault simulator is the type of faults which it models in the circuit. Only one type of fault has been considered in this project. This fault is modelled only on logic elements. For example, a stuck-at-1 fault on an input of an and gate means that no matter what kind of logic signal is driven into the faulted input, the effect on the output of the gate is that this input has always been a logical 1.

Splice is an electronic circuit simulation program in which the digital fault simulator was implemented as a feature. A serial algorithm was chosen, This is a relatively simple algorithm to implement and in comparison to other kinds of algorithms it takes longer to execute. This kind of fault simulator will take a relatively long time to run because it performs an entire simulation for every possible fault that could be present in the circuit. Before each simulation, the fault simulator modifies the data structure which represents the good circuit. This modification is to make the circuit that is to be simulated appear to have a particular fault present. After the circuit gets simulated, the results are compared to the results of an unfaulted-circuit simulation. If there are any significant differences in the two sets of results, then the fault simulator can deduce that the test pattern is good enough to detect the fault under consideration. The statistics for each run would be saved so that after all of the faults have been simulated, the fault simulator could make some kind of overall evaluation of the thoroughness and quality of the test pattern.


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This page was created on January 19, 1997 by Brent Petersen.
This page was updated on April 26, 2002 by Brent Petersen .
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