%%----------Chapter 2------------------------------------------
\chapter{System Design Process} \label{chap:Design} 

\section{Requirements Analysis}

In order to begin to design a testbed for wireless channel measurements, as with any other engineering endeavour, it is crucial to first understand the requirements for the final product. In this case, we were interested in building a radio testbed which would not only meet our requirement for a receiver implementation, but which would also provide a useful tool for future researchers to receive signals from commercial systems as well as test new theories and algorithms in an easily reconfigurable real-world environment. At the onset of system design, the best frequency band for experimental communication was chosen to be the 2.4~GHz ISM band due to the fact that it is freely available to use, provided that the requirements outlined in the Canadian Radio Standards Specification (RSS) RSS-210 are satisfied~\cite{rss210}.

\subsection{Design Decisions}

Based on the general objectives outlined above, some high-level design decisions were necessary in order to proceed with the hardware selection and system design stages. It was decided that it would be best to build the system from mostly commercial off-the-shelf (COTS) components in order to make the minimize the design time and reduce cost. Moreover, a modular system constructed of COTS components would allow a much greater degree of reconfigurability and interoperability than an application specific design. By selecting reconfigurable general purpose components, with standardized interfaces to interconnect to the rest of system, the system was made capable of supporting many different applications, including those using many frequency bands.

In order to enable the system to take advantage of SWAP gain, as well as the diversity gain and interference rejection capabilities of spatially multiplexed systems, it was decided that our testbed would be implemented as a MIMO system. To take advantage of ST techniques, without reaching the point of diminishing returns in terms of the number of antenna elements versus signal-to-noise ratio (SNR), and without exceeding our budget limitations, it was decided that our MIMO architecture would consist of four transmitters and four receivers (4x4).

Based on this decision it became clear that we would require the hardware to generate, as well as receive, four channels of data simultaneously. In keeping with the desire to conserve both time and financial resources, some components of the system were selected because they were already available in the department and had been used for previous work on the CNSR project. Two items purchased by a previous graduate student for his thesis work were of particular interest; specifically, two AOR AR5000AC wideband radio receivers and a Hittite direct quadrature modulator evaluation board. The AOR radio receiver was chosen to act as our RF receiver front-end partially to avoid having to create our own RF front-end. However, the main reason for choosing to use the AOR radio was due to its excellent features. The most important features for our application being: wideband frequency coverage from 10~kHz to 2600~MHz with no blocking of the cell band frequencies, selectable AGC function before the IF output, frequency locking capabilities to an external signal, RS-232 remote control of radio functions, and a relatively low second stage IF output at 10.7~MHz~$\pm$~5~MHz available before any processing is done on the data inside the radio; the first IF stage is at 622~MHz~\cite{aorMan}. The relatively low frequency IF output of the second stage is helpful because it greatly reduces the sampling rate required to digitize the received signal. \autoref{fig:AOR_Radio} shows the front panel of the AOR AR5000AC radio, while \autoref{fig:AOR_Radio_Schematic} shows the internal architecture of the radio.
\\ %insert a vertical space before the image
\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.15}{\includegraphics{./figures/AOR_Radio}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/AOR_Radio}
\caption{AOR AR5000AC Wideband Radio} \label{fig:AOR_Radio}
\end{center}
\end{figure}

\begin{figure}[!htbp]
\begin{center}
%\rotatebox{90}{\scalebox{0.80}{\includegraphics{./figures/AOR_Radio_Schematic}}}
\rotatebox{90}{\scalebox{0.8}{\includegraphics[height=\textwidth,keepaspectratio]{./figures/AOR_Radio_Schematic}}}
\caption{AOR AR5000AC Wideband Radio Schematic \cite{aorMan}} \label{fig:AOR_Radio_Schematic}
\end{center}
\end{figure}

The second available component, was a Hittite HMC497LP4 direct quadrature modulator evaluation board. This board, shown in \autoref{fig:HittiteEvalBoard}, performs a quadrature amplitude modulation (QAM) on a pair of input signals, inphase (I) and quadrature (Q). This board is capable of modulating (sine/cosine) incoming digital signals from DC~to~700~MHz onto a carrier sinusoid ranging from 100~to~4000~MHz with a typical gain of 5~deciBels (dB) relative to one milliwatt (dBm) or approximately 3.16~mW at 2.4~GHz~\cite{hittiteMan}. Due to the excellent capabilities of the Hittite evaluation board this is the choice for our RF transmitter front-end.
\\ %insert a vertical space before the image
\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.1}{\includegraphics{./figures/HittiteEvalBoard}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/HittiteEvalBoard}
\caption{Hittite HMC497LP4 Direct Quadrature Modulator Evaluation Board} \label{fig:HittiteEvalBoard}
\end{center}
\end{figure}

Once the selection of the RF transmit and receive front-ends was complete, the remainder of the system was designed around them. The choice of RF hardware imposed several design restrictions which were taken into account. The choice of radio receiver forced our work to be done at frequencies under 2.6~GHz, with a bandwidth no greater than 10~MHz, and analog-to-digital converters (ADCs) with sampling rates capable of digitizing the radios' IF output. Furthermore, the Hittite evaluation board limits the baseband inputs to less than 700~MHz and the carrier frequency to less than 4000~MHz. However, due to the radio bandwidth of 10~MHz, and tunable frequency range of 10~kHz up to 2.6~GHz, both of these factors are not of any consequence. Thus, there is no effective limitation due to the modulator.

In order to maximize the reconfigurability and usefulness of the testbed, the decision was made, from the onset, that the core of the design would be FPGA-based using software defined radio (SDR) techniques to process the signals in digital form at baseband. Moreover, we wanted the generation and later processing of the signals to both take place within the FPGA, in order to have the greatest degree of both control and configurability over the system. \autoref{tbl:fpgaVsMicroComparison} shows an up-to-date comparison between an FPGA device and a microprocessor. This highlights many of the excellent features of FPGA technology for DSP applications, which include much higher memory bandwidths, and data throughput, with a significantly lower clock speed. These results are possible due to the parallel capabilities of FPGA technology as compared to the sequential operation of a microprocessor. Do to the often parallel and high speed nature of many DSP applications, an FPGA architecture was chosen for this thesis.

\begin{table}
\begin{center}
\caption{FPGA vs. Microprocessor~\cite{Bo06}} \label{tbl:fpgaVsMicroComparison}
\begin{tabular}{|c|c|c|}%[t]
\hline
& Itanium 2 & Virtex 2VP100\\
\hline
\hline
Technology & 0.13 Micron & 0.13 Micron\\
\hline
Clock Speed & 1.6 GHz & 180 MHz\\
\hline
Internal Memory Bandwidth & 102 GB/s & 7.5 TB/s\\
\hline
Power Consumption & 130 W & 15 W\\
\hline
Peak Performance & 8 GFLOPS & 38 GFLOPS\\
\hline
Sustained Performance & ~2 GFLOPS & ~19 GFLOPS\\
\hline
I/O External Memory Bandwidth & 6.4 GB/s & 67 GB/s\\
\hline
\end{tabular}
\end{center}
\end{table}

Another useful feature we wanted to have for our system, was the ability to remotely control all parts of the system from a central FPGA. Thus, any further components selected needed some mechanism for remotely controlling them, preferably RS-232 due to the fact that the AOR radios have this built in, as well as the relative simplicity and widespread availability of RS-232 hardware.

To sum up the high-level design requirements, we wanted to build a 4x4 MIMO radio testbed from COTS components which is centrally controlled using FPGA technology to generate and process the signals. The system was required to be easily expandable and reconfigurable, while meeting our budget limitations. Furthermore, the system was required to take advantage of SWAP gain by separating the antennas on the scale of one signalling wavelength.

\section{\texorpdfstring{System Architecture Design and Hardware\\Selection}{System Architecture Design and Hardware Selection}}

With the goals previously outlined, the system architecture design along with the associated hardware selections necessary to meet the design goals, commenced. The following subsections describe the design of each of the subsystems along with explanations regarding any additional hardware selections.

\subsection{FPGA Development Platform}

The selection of FPGA hardware involves many choices. Currently, there are two main competitors in the mainstream FPGA chip manufacturing market, \alteraReg and \xilinxReg (listed alphabetically), with countless other companies developing FPGA development platforms based on their FPGAs. The challenge is not only to choose which FPGA chip manufacturer is best for your application, but also to try and locate a development platform which suits your needs. This can be extremely tedious because each company describes their FPGA chip features using their own proprietary architectures and their associated terminology which does not directly translate for easy comparison with that of their competitors. 

Based on the requirements of this thesis, and the best efforts of the author, two systems were found to have the most potential for use in the testbed design: an \alteraReg Digital Signal Processing (DSP) Development Board, and a LyrTech SignalMaster based system. At the core of the LyrTech system is the SignalMaster board which contains a \xilinxReg Virtex-II FPGA (up to XC2V8000), a Texas Instruments (TI) TMS320C6701 32-bit DSP which operates at 167~MHz, and up to 128~MiB of RAM to name but a few of its features. The SignalMaster board sits within a rack mount system and is connected to a central Compact PCI (cPCI) bus. Within the rack itself, there is a \pentiumReg~4 processor, a 20~GiB hard disk, and an Ethernet connection. The SignalMaster board itself does not have any analog inputs or outputs. To add these features additional boards are required, such as the VHS-ADC and VHS-DAC boards which respectively add up to sixteen 14-bit analog inputs (105 mega-samples per second (MSPS)) or outputs and connect to the system via the cPCI bus. On each of the VHS-ADC and VHS-DAC there is a \xilinxReg Virtex-II FPGA (Virtex-4 available on VHS-ADC at time of publishing), along with some onboard SDRAM~\cite{lyrAdcMan,lyrDacMan}. Indeed the LyrTech system has an incredible amount of processing power available to the user~\cite{lyrSigMan}.

The second potential solution is the \alteraReg \stratixReg II EP2S180 DSP Development Board. This board is a more general purpose FPGA board which contains the largest available \stratixReg II device from \alteraRegNS, 180~million logic elements. As well, the \alteraReg development board has a variety of external switches, LEDs, and interfaces for additional components. The board features two 12-bit 125~MSPS ADCs and two 14-bit 165~MSPS digital-to-analog converters (DACs). The \alteraReg FPGA development board provides 32~MiB of onboard SDRAM, a Compact Flash card slot which can be used to store user data, an Ethernet port, an RS-232 interface, and a minimum of 82~general purpose input/output (GPIO) pins which are user programmable. Furthermore, the \alteraReg board provides two dedicated connectors for connecting Analog Devices ADC evaluation boards, and a dedicated connector for interfacing a TI DSP evaluation board \cite{s2man}.

As one might expect, the LyrTech system is more expensive than the \alteraReg evaluation board, but also contains more processing power. It has the ability to support many more transmitters and receivers and is organized in a modular fashion which is consistent with the design objectives. It also has large amounts of disk space for recording data which could be useful for real-time applications as well as post-processing of data in an academic environment. To investigate the trade-off between the added complexity of the LyrTech system and the associated learning curve, the author arranged to borrow an evaluation system from LyrTech in order to give the system a trial run. Based on the two-week trial evaluation of the LyrTech system, as well as the previous generation of the \alteraReg system (DSP Development Kit, Stratix Professional Edition), available in the lab, a number of important points were noted. 

At the time, the added features of the LyrTech system only added to the complexity of using it, especially at a low level. The system is meant to be used with the \matlabReg \simulinkReg package. Development using the standard \xilinxReg development environment required that the user try to control the many different interactions among the various I/O standards, buses, and devices in the system. LyrTech did provide drivers for these tasks, however a substantial amount of work would be required in order to fully understand and take advantage of the many different modules. In the case of the \alteraReg development board, there was only one FPGA device, albeit very large, which limited the design possibilities but which also kept the degree of complexity to a minimum. The development environment for the \alteraReg development board is the developers choice of either \simulinkReg or \quartusReg~II, \alteraRegPL proprietary development environment. Through the testing experience, the author found that the \simulinkReg software package was indeed a very powerful tool for designing and simulating at a high level, but not without a cost. \simulinkReg basically acts as a modelling environment in which the designer can create a design and simply tell the software to generate code for the design. The code created by \simulinkReg is more like machine code and not easily readable, which leads one to wonder how difficult it would be to uncover a bug in the design at a low level. The \simulinkReg tools add another layer of complexity on top of the already growing stack of new knowledge for a beginner to learn in a short period of time. Having said that, it is the opinion of the author that a user who is well acquainted with using \simulinkReg might have the upper hand, in terms of time spent developing, on a user who is designing at a lower level.

Based on the experience gained through the trial evaluations of the two FPGA development systems, the following conclusions were made. For a new user and for the purposes of the work in this thesis, the inherent complexity of the LyrTech system along with the need to work with \simulinkRegNS, created a learning curve above and beyond the initial time involved with learning FPGA design and hardware design language implementation. The LyrTech system provided eight ADCs and eight DACs in the default configuration, whereas the \alteraReg system only provided two of each. However, due to the fact that the \alteraReg system was available for a lower cost than the LyrTech system, coupled with its many available GPIO pins, two \alteraReg FPGA boards can easily be doubled up at a lower cost than a single LyrTech system. That is, two \alteraReg FPGA development boards can be interconnected to provide a system with two large FPGAs, four ADCs, and four DACs. The DACs on the \alteraReg board are faster than those on the LyrTech VHS-DAC board, however the ADCs are only 12-bits, compared to the 14-bit ADCs on the LyrTech VHS-ADC board. In any software defined radio system, the ADCs and DACs play a crucial role and are of paramount importance because they effectively govern the overall system performance~\cite{icsANSR2}. Furthermore, the LyrTech system has an onboard DSP processor which could be useful for baseband algorithms and control functions. The \alteraReg system can counteract both of these factors thanks to its dedicated connectors for two ADCs and a DSP. By coupling two \alteraReg boards, four external Analog Devices AD6645 evaluation boards, the same ADC as on the SignalMaster, and a TI DSP evaluation board, the \alteraReg board overcomes the most crucial hardware differences between the two systems. Moreover, the size of the LyrTech system (rack mount) severely limits its mobility, which is a crucial point given that radio channel measurements will likely have to be taken outdoors given the large antenna separations required for SWAP gain and the desire for LOS testing.

For the aforementioned reasons as well as the fact that the \alteraReg system meets the design requirements and was available at a lower cost than the LyrTech system, the decision was made that we would purchase the \alteraReg hardware for the thesis. Another factor which contributed to this decision was that several other students in the department were also working with similar \alteraReg hardware and the \quartusReg II software package. The LyrTech system, which is \xilinxReg based, is an excellent product, but in the opinion of the author would be more suitable for a dedicated non-mobile application requiring large amounts of processing power such as a base station.

\autoref{fig:AlteraFPGA_Features} illustrates the \alteraReg \stratixReg~II EPS2180 DSP Development Kit along with many of its main hardware features. Note that the connector for the TI DSP is on the bottom side of the board.

\begin{figure}[!htbp]
\begin{center}
%\rotatebox{90}{\scalebox{0.60}{\includegraphics{./figures/AlteraFPGA_Features}}}
\rotatebox{90}{\scalebox{1}{\includegraphics[height=\textwidth,keepaspectratio]{./figures/AlteraFPGA_Features}}}
\caption{\alteraReg \stratixReg II EP2S180 DSP Development Kit \cite{s2man}} \label{fig:AlteraFPGA_Features}
\end{center}
\end{figure}

\subsection{Transmit Side}

To meet the requirements of a 4x4 MIMO array, the system must be able to produce four signals to transmit. Each transmitter represents a single user in the system, enabling our system to simulate up to four simultaneous users at a time. As mentioned earlier, the signal generation is done within the FPGA board. Note that since the Hittite direct quadrature modulator board accepts inphase and quadrature signals for each user, it is necessary to generate two signals for each of the four users; that is, four pairs of I and Q signals. For testing purposes, it is useful to know exactly what the transmitted signal was, in order to facilitate the recovery of the received signals through demodulation and equalization. To meet this need, eight linear recursive sequence (LRS) generators with different tap configurations can be used to generate a known distinct pair of I and Q signals for each user. Circuits to generate LRS sequences are relatively straightforward to implement in the FPGA, and the resulting bit streams can be output to the Hittite modulator boards using eight GPIO pins on the development board. 

Ideally, the generated signals would be output from  the FPGA boards to the Hittite modulator board using the onboard DACs. This would allow digital pulse shaping filters, such as a raised cosine, to be applied to the data stream inside the FPGA before transmission. However, due to the fact that we only have four DACs (two per \alteraReg board), we are forced to output the signals as purely digital waveforms in order to meet the goal of a 4x4 MIMO array. The advantage of using a rectangular pulse shape is that there is no intersymbol interference (ISI) since the pulse does not extend beyond its own interval. However, the Fourier transform of a square, or rectangular, function in time is a sinc pulse of infinite bandwidth in frequency, and as a result the rectangular pulse is not a particularly good choice for a communication system because it wastes bandwidth. A raised cosine pulse, in the frequency domain, on the other hand, has the advantage of limiting bandwidth while decaying quickly and having zeros crossing at the sampling instants~\cite{Gen02}. To generate a raised cosine pulse, a damped sinc function is used in the time domain as shown in \autoref{eqn:RaisedCosinePulse}~\cite{proakisDigiComm},

\begin{equation} \label{eqn:RaisedCosinePulse}
x(t) = \left(\frac{\sin{\frac{\pi t}{T}}}{\frac{\pi t}{T}}\right) \left(\frac{\cos{\frac{\beta \pi t}{T}}}{1-\frac{4 \beta^{2} t^{2}}{T^{2}}}\right).
\end{equation}
\\
The variable $\beta$, $0 \leq \beta \leq 1$, is called the rolloff parameter or damping coefficient. As $\beta$ increases, the time-domain response decays more rapidly, however the frequency domain raised cosine re\-sponse band\-width in\-creases~\cite{Gen02}. \autoref{fig:RaisedCosineCurves} illustrates this tradeoff.

\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.35}{\includegraphics{./figures/RaisedCosineCurves}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/RaisedCosineCurves}
\caption{Raised Cosine Curves \cite{proakisDigiComm}} \label{fig:RaisedCosineCurves}
\end{center}
\end{figure}

Due to the modular design of the system, the ability to use pulse shaping filters can be added at a later time by either adding two additional ADCs, or performing the modulation within the FPGA and then mixing it with the carrier externally. The latter would require only one DAC per user signal, both I and Q. With the current hardware we can support up to four users using this technique.

Once the digital signals have been created and output from the FPGA, all that is left is to modulate the data onto a 2.4~GHz carrier waveform and radiate it via the transmit antennas. As mentioned earlier, the Hittite HMC497LP4 direct quadrature modulator boards are used to modulate the data stream onto the carrier. To provide a carrier signal in the 2.4~GHz ISM band, such as 2.45~GHz, the Aeroflex 2025 AM/FM signal generator shown in \autoref{fig:Aeroflex2025} was chosen, and purchased, based on its rich feature set and relatively low cost. As per the system requirements, it can generate signals from 9~kHz up to 2.51~GHz, covering the 2.4 GHz ISM band, and also provides RS-232 remote control functionality for all features, excluding the power button. As well, the signal generator provides a high stability 10~MHz frequency standard output which is used to synchronize the entire system~\cite{aeroflexMan}.
\\ %insert a vertical space before the image
\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.15}{\includegraphics{./figures/Aeroflex2025}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/Aeroflex2025}
\caption{Aeroflex 2025 AM/FM Signal Generator} \label{fig:Aeroflex2025}
\end{center}
\end{figure}

Thus, modulation of the transmit signal can be achieved by applying the digital data streams generated within the FPGA board, along with the 2.4~GHz carrier sinusoid from the signal generator to the appropriate inputs of the Hittite modulator board. However, in order to interface the eight FPGA GPIO pins to the Hittite vector modulators, some voltage translation is required. Specifically, the FPGA board output uses the low voltage transistor-transistor logic (LVTTL) standard 0-3.3~V~\cite{s2man}, whereas the Hittite vector modulator requires a 1.6~Volt peak-to-peak ($V_{pp}$) input with a 1.5~Volt direct current ($V_{DC}$) offset~\cite{hittiteMan}. To achieve the required translation, a custom printed circuit board (PCB) was necessary. The design and fabrication of this board is described in the implementation section in \autoref{chap:Implementation}. A simplified block diagram of an individual transmitter is shown in \autoref{fig:TransmitterDesign}. Note that since only one Hittite modulator board was available, it was necessary to purchase three additional units. 
\\ %insert a vertical space before the image
\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.7}{\includegraphics{./figures/TransmitterDesign}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/TransmitterDesign2}
\caption{Simplified Transmitter Structure} \label{fig:TransmitterDesign}
\end{center}
\end{figure}

Note that each of the I and Q signals are effectively a pair of binary phase shift keying (BPSK) signals which, when modulated, produce a 4-QAM constellation with I on the horizontal axis and Q on the vertical axis. The location of each of the transmit antennas is midway between each of the receive antennas, approximately 60~meters away from the centre of the array.

\subsection{Receive Side}

As with the transmit side, the receive side of the system consists of four identical circuits for receiving data. These receivers provide four channels of incoming RF data to be processed by the system. In order to simplify the RF front-end design of our receivers, we are using four AOR AR5000AC wide band all-mode receivers. This required that two additional radio receivers be purchased for the thesis, to supplement the two that were already in our possession. The RF signals which arrive at each of the four receive antennas are down-converted to 10.7~MHz using the AOR radios, which provide a 10~MHz bandwidth IF output centered at 10.7~MHz.

Sampling of the IF signals is performed using four Analog Devices AD6645/ PCB daughter boards, shown in \autoref{fig:AD6645_EvalBoard}, which have special headers allocated to them on the \alteraReg \stratixReg II DSP Development Board. This allows two channels of incoming data to be received by each \alteraReg Development Board. The sampling rate of the ADCs is greater than 31.4~MHz in order to satisfy the Nyquist criterion. The conversion clock is provided by the FPGAs.
\\ %insert a vertical space before the image
\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.15}{\includegraphics{./figures/AD6645_EvalBoard}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/AD6645_EvalBoard}
\caption{Analog Devices AD6645/PCB Evaluation Board} \label{fig:AD6645_EvalBoard}
\end{center}
\end{figure}

To avoid synchronization issues, each of the four AOR radios as well as the two \alteraReg FPGA boards are locked to a common 10~MHz reference. The common reference signal for the entire system comes from the Aeroflex signal generator and is provided in order to frequency lock each of the four radios as well as the FPGA circuitry. AGC is provided by the AOR radios. \autoref{fig:ReceiverDesign} illustrates the basic structure of each of the four receivers.

\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.7}{\includegraphics{./figures/ReceiverDesign}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/ReceiverDesign}
\caption{Simplified Receiver Structure} \label{fig:ReceiverDesign}
\end{center}
\end{figure}

The SNR, or dynamic range (DR), of a digital receiver can be calculated as shown in \autoref{eqn:SNR}, where $N$ is the number of bits in the ADC. Note that $f_{s}$ is the sampling frequency of our ADCs and $B$ is the passband bandwidth, 10~MHz in this case. Ten times the log of the ratio of $f_{s}/2$ over $B$ is called the processing gain (PG), in dB. From this relationship, it is clear that as $f_{s}$ is increased beyond twice the passband bandwidth of $2 B$, the SNR increases. This is due to the effect of spreading the quantization noise power over the bandwidth~\cite{maximAN728,maximAN928}.
\begin{equation} \label{eqn:SNR}
SNR_{dB} = DR_{dB} = 6.02 N + 1.76 + 10 \log_{10}{\left(\frac{f_s}{2 B}\right)}
\end{equation}

Ignoring the processing gain portion for the time being, the SNR for our receiver can be roughly approximated to 86.04~dB, above the quantization noise, as shown in \autoref{eqn:SNR_Simplified}. By oversampling the data the quantization noise is spread over a greater frequency range, resulting in a processing gain of 6.02~dB as shown in \autoref{eqn:ProcessingGain}. Thus, the total estimated dynamic range of the system is 92.06~dB.
\begin{equation} \label{eqn:SNR_Simplified}
\begin{split}
SNR_{dB} = DR_{dB} &= 6.02 N + 1.76\\
&= 6.02\times{14}+1.76\\
&= 86.04~\mathrm{dB}
\end{split}
\end{equation}

\begin{equation} \label{eqn:ProcessingGain}
\begin{split}
PG_{dB} &= 10 \log_{10}{\left(\frac{f_s}{2 B}\right)}\\
&= 10 \log_{10}{\left(\frac{80}{2\times{10}}\right)}\\
&= 6.02~\mathrm{dB}
\end{split}
\end{equation}

Although this is a rough theoretical approximation of the best case scenario, our ADCs coupled with the AGC capabilities of the AOR radio receivers should provide more than enough dynamic range.

Identical antennas were chosen for both of the transmitters and receivers. For this we selected Antenna Factory FO2400-8 vertical antennas with a gain of 8~dB relative to isotropic (dBi) and 83~MHz of bandwidth from 2.4-2.483~GHz, covering the 2.4~GHz ISM band~\cite{ant2400man}. As well, four Antenna Factory \mbox{FO1710-8} vertical antennas with a gain of 8~dBi and frequency coverage from 1710-1990~MHz were purchased for receiving signals from commercial systems in the 1900~MHz range, although they are not used in this design~\cite{ant1710man}. \autoref{fig:Antenna_2400MHz} shows the antennas which are used in this design for signalling in the ISM band, they are 0.6~m long. Note that the receive antennas are spaced 60~m apart from one another, and are connected to the central hub using coaxial cable, in order to take advantage of SWAP gain.
\\ %insert a vertical space before the image
\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.15}{\includegraphics{./figures/Antenna_2400MHz}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/Antenna_2400MHz_ruler}
\caption{Antenna Factory F02400-8 Antenna} \label{fig:Antenna_2400MHz}
\end{center}
\end{figure}

\subsection{Baseband Processing}

Once the IF signal has been sampled, processing within the FPGA can begin. A 5.7-15.7~MHz bandpass finite impulse response (FIR) filter removes any unwanted spectrum, followed by a demodulator circuit and a ST receiver, using the least mean square (LMS) adaptive algorithm to equalize the channel, reduce interference, and recover each user's transmission. In order to achieve this, the ST array design consists of four groups of four adaptive filters. Each of the four filters, within a single group, connects to a different receive antenna input, and each particular group is trained to isolate the signal of only one user in the system. The outputs of each of the four adaptive filters, in a particular group, are then combined to average the signals from the four antennas. This limits the number of users in the system to four, but provides diversity gain over the single antenna case. The ST receiver structure design which is implemented for this system is described by Paulraj et al.~\cite{paulrajSTcomm}, and is illustrated in \autoref{fig:ST_Receiver}.
\\ %insert a vertical space before the image
\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.55}{\includegraphics{./figures/ST_Receiver}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/ST_Receiver_lighter}
\caption{Space-Time Receiver Structure} \label{fig:ST_Receiver}
\end{center}
\end{figure}

\subsection{Centralized Control}

The addition of a TI~6416 1~GHz fixed point DSP is intended to facilitate control algorithms and perhaps some low speed signal processing at baseband.

In order to achieve central control over the entire functionality of the system, the FPGAs need to be able to communicate with each of the individual COTS components in the design. The first step in designing this control system was to select components which can be remotely controlled via RS-232. The \alteraReg FPGAs each have one RS-232 port, however there is a need to control at least five different devices simultaneously -- four radios and the signal generator. To meet this need, a \blackBoxReg SWE-854A-R2 (COS-8P) 8-port Code Operated Switch (COS), as shown in \autoref{fig:BlackBoxCOS}, was selected. This device allows one master to control up to eight slaves by controlling which slave is connected at any particular time. To control the switching between slaves, the master transmits a code word, which will not appear in the data stream, followed by a number indicating to which slave it would like to communicate. As such, it is possible to uniquely address each of the components, which enables remote control access to all the features of the radios and the signal generator. Unfortunately, the ability to broadcast the same message to multiple slaves is not available. Instead, each slave has to be addressed and signalled separately. The average time required to switch between slaves has been quoted by \blackBoxReg technical support to be no greater than 10~ms~\cite{BlackBoxMan}. The details regarding the configuration of the switch are provided in the implementation section. 
\\ %insert a vertical space before the image
\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.15}{\includegraphics{./figures/BlackBoxCOS}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/BlackBoxCOS}
\caption{\blackBoxReg SWE-854A-R2 8-Port COS} \label{fig:BlackBoxCOS}
\end{center}
\end{figure}

Since we also control the baseband transmit and receive functions directly via the FPGA, this provides complete control over the system. Advanced testing techniques such as swept frequency, for instance, can be achieved by simply sweeping the tuned frequency of the radio receivers across the frequency spectrum of interest. \autoref{fig:CentralControl} illustrates the baseband side of the system and how it interacts with and controls the rest of the hardware in the system.
\\ %insert a vertical space before the image
\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.75}{\includegraphics{./figures/CentralControl}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/CentralControl2}
\caption{Central Control Structure} \label{fig:CentralControl}
\end{center}
\end{figure}

Due to the fact that our antenna array is spread over such a large area, several issues arise. Firstly, the location of each of the components becomes important. Since the incoming data rate to both the receive and transmit antennas is 2.4~GHz, there would be a significant amount of attenuation over 60~meters of coaxial cable. To avoid this problem, both the AOR radios and the Hittite vector modulator boards are situated close to their respective receive and transmit antennas. Thus, the signals travelling through the 60 meter run of coaxial cable will be at the IF frequency of 10.7~MHz which, coupled with low loss cabling, is acceptable. The tradeoff of this decision is that the RF equipment must now be situated remotely at each of the eight antennas.

The second issue derives from the solution to the first issue, and our desire to control the array centrally. In order to synchronize all the AOR radios, a 10~MHz reference signal must be shared amongst them. Furthermore, centralized control over these radios requires that each have an RS-232 connection to the central hub. This translates to two 60~m runs of coaxial cable, plus one 60~m run of RS-232 cable per receive antenna. Combined with the I and Q, and 2.4~GHz reference signals sent to each transmit antenna, three 60~m runs of coaxial cable, the grand total comes to 1200~m of coaxial cable plus 240~m of RS-232 cabling. \autoref{fig:TestbedTopology} shows the topology of the array along with the signals which are sent amongst the various components. Note that this figure is not to scale.

\begin{figure}[!htbp]
\begin{center}
%\rotatebox{90}{\scalebox{0.8}{\includegraphics{./figures/TestbedTopology}}}
\rotatebox{90}{\scalebox{1}{\includegraphics[height=\textwidth,keepaspectratio]{./figures/TestbedTopology2}}}
\caption{Testbed Topology} \label{fig:TestbedTopology}
\end{center}
\end{figure}

\subsection{Testing and Debugging Equipment}

To facilitate the testing and debugging process, a Lecroy WaveSurfer~424 200~MHz 2 GSPS oscilloscope was borrowed from another lab. As well, an AOR SDU~5600 fast Fourier transform (FFT) spectrum display unit which is designed to interface to and be controllable by the AOR AR5000AC radios, was purchased. This device can also work as a standalone unit.
