%%--------------------Chapter 3------------------------
\chapter{System Implementation} \label{chap:Implementation}

This chapter describes the implementation specific details of the system design described in \autoref{chap:Design}, and as such, it is broken down in a similar fashion. The system was developed using the Verilog hardware description language (HDL) using the \alteraReg \quartusReg~II (version~5.1 service pack~1) development environment. The choice of Verilog was based solely on the fact that the author had prior experience with that language. It should be noted that this choice is not in any way a tradeoff, and that any future additions to the system can be written in either Verilog or Very-High-Speed Integrated Circuit HDL, more commonly known as VHDL.

\section{Transmit Side}

\subsection{Data Generation}

The first stage of development for the system was to be able to generate signals for transmission. As mentioned earlier, LRS generators are used to create predetermined random bit streams, otherwise known as pseudorandom noise (PN) sequences. Such circuits can be easily constructed using a shift register constructed of D flip-flops with configurable feedback taps. As implied by the name, the sequences in fact appear to be random and have the same basic properties, but are fixed in both bit sequence and length. The bit sequence is determined by both the feedback tap connections and the length of the shift register. The bit sequence is not infinitely long however, it repeats at predefined intervals. In the ideal PN generator, the sequence is of length $2^{N}-1$, where $N$ is the number of flip-flops in the shift register. In this case, the sequence is called a maximal length sequence. A maximal length sequence can only be created by using a feedback tap polynomial which is a primitive prime~\cite{notesDigiComm}. The following definition holds of primitive prime polynomials, ``For a prime $P(x)$ to give a maximum length sequence of length $L$, $P(x)$ must be a factor of $x^{L}+1$ (and of no other smaller $L$). Such a prime is called primitive''~\cite{notesDigiComm}. In order to ensure that the ST receiver would have enough time to train properly, we chose to use tenth order primitive prime polynomials which result in a maximal length sequence of $2^{10}-1=1023$ bits. \autoref{tbl:ppGenPolynomials} lists the primitive prime generating polynomials used in the system design, although any can be used. Note that this is not an exhaustive list. A complete table of irreducible polynomials over Galois fields GF(2), the binary case, through GF(5) up to order eleven can be found in Church's ``Tables of Irreducible Polynomials for the First Four Prime Moduli''~\cite{Ch35}.
\\ %insert a vertical space before the table
\begin{table}[!htbp]
\begin{center}
\caption{Primitive Prime Generating Polynomials \cite{Ch35}} \label{tbl:ppGenPolynomials}
\begin{tabular}{|c|c|}
\hline
%\multicolumn{2}{|c|}{Generating Polynomials}\\
%\hline
Polynomial& Tap Configuration\\
\hline
\hline
$x^{10}+x^{3}+1$& (10,3,0)\\
\hline
$x^{10}+x^{4}+x^{3}+x+1$& (10,4,3,1,0)\\
\hline
$x^{10}+x^{5}+x^{2}+x+1$& (10,5,2,1,0)\\
\hline
$x^{10}+x^{5}+x^{3}+x^{2}+1$& (10,5,3,2,0)\\
\hline
$x^{10}+x^{6}+x^{5}+x^{2}+1$& (10,6,5,2,0)\\
\hline
$x^{10}+x^{6}+x^{5}+x^{3}+x^{2}+x+1$& (10,6,5,3,2,1,0)\\
\hline
$x^{10}+x^{7}+1$& (10,7,0)\\
\hline
$x^{10}+x^{7}+x^{3}+x+1$& (10,7,3,1,0)\\
\hline
\end{tabular}
\end{center}
\end{table}

Based on these generating polynomials, it is relatively straightforward to develop an LRS generator circuit in Verilog. \autoref{fig:lrsCircuit} shows the basic architecture of the circuit for the generating polynomial $x^{10}+x^{3}+1$. The source code for this module can be found in \autoref{appendix:DesignCode} and on the enclosed CD-ROM.
\\ %insert a vertical space before the image
\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.525}{\includegraphics{./figures/PNGenerator}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/PNGenerator2}
\caption{LRS Generator Circuit Architecture} \label{fig:lrsCircuit}
\end{center}
\end{figure}

\subsection{\texorpdfstring{FPGA Interfacing to the Hittite Modulator\\Board}{FPGA Interfacing to the Hittite Modulator Board}}

Once the user signals have been generated within the FPGA, they are output using GPIO pins to the Hittite modulator board. However, in order to interface the LVTTL, 0-3.3~V output from the FPGA, to the requirements of the Hittite modulator board of $1.5~V_{DC} + 1.6~V_{AC}$, a custom interface board was needed. Since the modulator board is situated near the transit antennas, at the far end of 91.4~m, or 300~feet, of cable, the signal conditioning circuitry does not only have to meet the level translation requirements, but also handle the drive current requirements. The design choice of 300~foot cable lengths is discussed in \autoref{sec:Cabling}. Based on these requirements, a simple resistive network was selected and designed such that it would provide the necessary voltage translation and also appear as a 50~$\Omega$ input looking inward at the cable. \autoref{fig:SigCondCircuit} illustrates the final resistive network design, along with the DC bias point simulation numbers. The circuit was simulated using \pspiceRegNS.

\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.275}{\includegraphics{./figures/SigCondCircuit}}
\rotatebox{90}{\scalebox{0.5}{\includegraphics[height=\textwidth,keepaspectratio]{./figures/SigCondCircuit}}}
\caption{FPGA to Hittite Signal Conditioning Circuit} \label{fig:SigCondCircuit}
\end{center}
\end{figure}

The input to the resistive divider circuit is driven through a TI SN74\-ALB\-16244 16-bit buffer/driver which provides up to 25~mA source and sink currents~\cite{tiBufferMan}. This easily meets the circuit requirements of 7.3~mA sink and 0.8~mA source (see \autoref{appendix:BoardDesigns} for details). As well, the voltage output of the buffer chip was measured, under real-world operating conditions, to be 0.3~V for logic low and 2.3~V for logic high. This was accounted for in the circuit design in order to ensure that the output met the specifications needed. The \pspiceReg simulation output, GPIO pins used, PCB schematic, and board layout are located in \autoref{appendix:BoardDesigns}. \autoref{fig:SigCondPCB} shows the finished circuit board mounted atop the GPIO header on the \alteraReg FPGA board. The eight SMA connectors situated at the top of the figure are the inphase and quadrature signal outputs, while the four SMA connectors on the right side of the board are the clock output signal to the external AD6645 ADC boards.

\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.3}{\includegraphics{./figures/SigCondPCB}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/SigCondPCB}
\caption{FPGA to Hittite Signal Conditioning PCB} \label{fig:SigCondPCB}
\end{center}
\end{figure}

\matlabReg analysis of the Hittite modulator board, revealed that the inphase and quadrature components of the received signal were only 45~degrees out of phase rather than 90~degrees. Debugging efforts along with communications with Hittite technical support, showed that the setup of the board was incorrectly performed by previous users of the hardware. In fact, the 1.5~$\mathrm{V_{DC}}$ signal should be a common mode signal shared between both the negative and positive differential baseband I and Q inputs, as opposed to the single ended use in previous work -- although this is not at all apparent from reading the board datasheet. To accommodate for this inconsistency, a second PCB board was constructed which provides a 1.5~$\mathrm{V_{DC}}$ output along with 1~$\mu$F terminating capacitors to ground for driving the $I_{n}$ and $Q_{n}$ negative inputs. As well, the negative RF input, $\mathrm{RF_{n}}$, requires a large terminating capacitor based on the local oscillator (LO) frequency. In this case our LO is 2.4~GHz and as such, Hittite technical support recommended using a 100~pF terminating capacitor~\cite{hittiteTechSupportPrivComm}. The bias circuit schematic can be found in \autoref{appendix:BoardDesigns}. \autoref{fig:HittiteBiasCircuitBoard} shows the finished board. In order to provide the bias signals to each of the Hittite boards, four such circuits are needed in total. At the present time, only one has been completed, however they are relatively simple to replicate on a copper prototyping board. Note that the 2.4~GHz carrier signal will be sent to each of the Hittite modulator boards using coaxial cables. At this frequency there would be a great deal of attenuation of the signal. This was overcome by using a \minicircuitsReg ZX10-4A-27+ 4-way power divider and simply increasing the gain at the signal generator end.
\\ %insert a vertical space before the image
\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.15}{\includegraphics{./figures/HittiteBiasCircuitBoard}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/HittiteBiasCircuitBoard}
\caption{Hittite Bias Circuit Board} \label{fig:HittiteBiasCircuitBoard}
\end{center}
\end{figure}

Testing of the Hittite board, after the addition of the bias circuit, confirmed that the problem was solved and that the inphase and quadrature signals were now being correctly modulated onto the carrier.

\subsection{Data Rate Calculation}

Recall that $\beta$ represents the rolloff factor for a raised cosine response. From \autoref{eqn:RaisedCosinePulse}, note that when $\beta$ is one, the equation reduces down to that of a square wave~\cite{La02}, which is the case for this design. This leads to another important factor in communications systems -- the excess bandwidth. The excess bandwidth is a measure of the amount of bandwidth, above the Nyquist bandwidth, which is being used to transmit the data. The amount of bandwidth used for transmitting data can be calculated as shown in \autoref{eqn:ExcessBandwidth}, where $W_{0}$ is the utilized bandwidth, and $R_{s}$ is the symbol rate. The excess bandwidth is simply $\beta\times{100\%}$~\cite{La02}
\begin{equation} \label{eqn:ExcessBandwidth}
W_{0} = (1+\beta)R_{s}.
\end{equation}

Given that $\beta$=1, for a square wave, and that $W_{0}$ cannot exceed 10~MHz, the symbol rate is found to be 5~MSPS. Using 4-QAM modulation, each symbol represents two bits, 2 bits/symbol, which corresponds to 10~Mbps at a symbol rate of 5~MSym/s, 5 Mbps on I and Q channels, and 100\% excess bandwidth. In the ideal case where sinc functions were transmitted as data, $\beta$ would be 0, which corresponds to 0\% excess bandwidth. In this idealized case, the maximum throughput rate of the system would be 10~MSym/s, or 20~Mbps.

\section{Receive Side}

\subsection{Clock Distribution}

The implementation of the receive hardware is intricately related to the distribution and synchronization of clocks throughout the system. In order to simplify the signal recovery process, it was decided that a single clock source would be used to trigger the entire system -- transmit, receive, and baseband processing subsystems. To achieve this goal, the 10~MHz reference signal from the Aeroflex signal generator is divided amongst the FPGA boards and the four radios in the system. Note that the FPGA outputs clock signals, corresponding to the sample rate clock, to the ADC boards, using the four dedicated SMA outputs on the Hittite signal conditioning circuit, and thus providing user programmable sampling rates; see \autoref{sec:ImplBasebandProcessing} for details. The reference signal from the signal generator has a range of $\pm1~\mathrm{V_{pp}}$ into 50~$\Omega$~\cite{aeroflexMan}. By direct observation, it was found that this signal level was acceptable to drive the frequency standard inputs of the AOR radios sufficiently enough to allow the internal phase locked loop (PLL) to lock. However, in the case of the FPGA board, the clock input pin uses the LVTLL standard which certainly cannot handle a negative input. As such, another custom PCB interface board was designed. In this case the design consists of a single chip, a TI TLV3501 high-speed comparator, which performs level translation on the incoming clock signal from the signal generator so that it can be input into the FPGA. This device basically compares the incoming signal to a reference signal, 0~V in this case, and outputs the value provided for logic high, 3.3~V in this case, if the incoming signal exceeds the reference, otherwise it outputs a logic low, 0~V in this case. For this application, the reference voltage was set to 0 V, the upper voltage reference was set to 3.3 V, and the lower reference was set to 0~V. Thus, when the $\pm1~V_{pp}$ input clock signal exceeds 0~V, the TLV3501 outputs 3.3~V, and when the clock signal is less than 0~V, it outputs 0~V. This device was specifically chosen for its low rail-to-rail propagation delay of 4.5~ns which easily meets the needs of the 10~MHz clock signal with a corresponding period of 10~$\mu$s~\cite{compMan}. The comparator circuit schematic and board layout can be found in \autoref{appendix:BoardDesigns}. \autoref{fig:ClockComparatorPCB} shows the finished clock signal level translator~board.

\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.15}{\includegraphics{./figures/ClockComparatorPCB}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/ClockComparatorPCB}
\caption{Clock Signal Level Translator PCB} \label{fig:ClockComparatorPCB}
\end{center}
\end{figure}

As the number of radios connected to the output of the signal generator frequency standard increases, the signal becomes more and more attenuated, at a theoretical rate of 3~dB per split. As it turns out, after the FPGA and two radios are connected, the signal attenuates to the point that the radios lose their PLL lock. To overcome this issue, a variable gain amplifier is required to boost the signal strength. This component has not been purchased yet, but the amplifier requirements have been evaluated by using a fixed gain amplifier which is prescaled by a variable attenuator in order to achieve the correct output gain. The attenuator is a Kay Electric model 30-0, and the amplifier is a \minicircuitsReg ZHL-6A with a typical fixed gain of 25~dB~\cite{ampMan}. \autoref{tbl:reqGainForRadios} lists the observed gains required as each additional radio was added to the system; the FPGA is always connected.
\\ %insert a vertical space before the table
\begin{table}[!htbp] 
\begin{center}
\caption{Required Gain for Radio PLL Lock} \label{tbl:reqGainForRadios}
\begin{tabular}{|c|c|c|c|}
\hline
%\multicolumn{2}{|c|}{Generating Polynomials}\\
%\hline
Number of Radios& Attenuation (dB)& Gain (dB)& Effective Gain (dB)\\
\hline
\hline
1& 25& 25& 0\\
\hline
2& 20& 25& 5\\
\hline
3& 17& 25& 8\\
\hline
4& 15& 25& 10\\
\hline
\end{tabular}
\end{center}
\end{table}

It should be noted that the AOR radios do not have 50~$\Omega$ frequency standard inputs. Although not mentioned in the AOR documentation, they are actually high impedance which results in significant reflections when the cables are not terminated. As such, the above discussion assumes that the clock input to each radio passes though a 50~$\Omega$ feed-through terminator. For the purposes of testing this portion of the system, borrowed terminators were used. In the future, four such terminations will have to be purchased. \autoref{fig:ClockInterconnections} illustrates the clock distribution scheme, external to the FPGA, for the system.

\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.6}{\includegraphics{./figures/ClockInterconnections}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/ClockInterconnections}
\caption{System Clock Interconnection Architecture} \label{fig:ClockInterconnections}
\end{center}
\end{figure}

\subsection{Sampling the Data}

To meet the Nyquist criterion for sampling the incoming IF data, the sampling rate must be greater than 31.4~MHz. However, it is in our interest to have a high sampling rate in order to take advantage of processing gain and then to later decimate the signal. Based on this concept, a sampling rate of 80~MHz was selected during the system design. Note that this value is configurable and is not permanently fixed at 80~MHz.

Within the FPGA, the 10~MHz reference frequency is multiplied by eight using a PLL to generate an 80~MHz sample clock for the ADCs. The sampled data from each ADC is passed through a ribbon cable back to the FPGA -- two ADCs per FPGA.

\section{Baseband Processing} \label{sec:ImplBasebandProcessing}

The baseband processing portion of the system comprises the two FPGAs, and four ADC boards. In order to make the system more portable and safe to use outdoors, the baseband components were mounted onto a wooden board using standoffs. \autoref{fig:BasebandProcessingHardware} shows the mounted FPGA and ADC boards.

\begin{figure}[!htbp]
\begin{center}
%\rotatebox{90}{\scalebox{0.15}{\includegraphics{./figures/BasebandProcessingHardware}}}
\scalebox{0.7}{\includegraphics[width=\textwidth,keepaspectratio]{./figures/BasebandProcessingHardware2}}
\caption{Mounted Baseband Processing Hardware} \label{fig:BasebandProcessingHardware}
\end{center}
\end{figure}

The ADC boards require +3.3~V, +5~V, -5~V, and GND power connections. The power for these boards is provided using a PC power supply which was modified for this design to operate as a standalone power supply. The power supply connects to the wooden mounting boards via the ``banana connectors'' located at the top of the board. The power connections are run as a bus, underneath the mounting board using a routed out groove, and then pass through holes to the top of the board where they connect to each of the ADC boards. The list of modifications made to the power supply can be found in \autoref{appendix:PowerSupplyMods}.

The basic goal of this thesis was to build a testbed system. The baseband processing portion of this design implements the demodulation of the incoming data stream, but leaves all future additions up to the developer. That is, the system is responsible for generating the data and recovering it back on the receive side. 

\subsection{Data Recovery and Demodulation}

The spectrum of the sampled data from the ADCs, shown in \autoref{fig:fft_sampled_data}, shows that the recovered signal is very well contained within the passband and that there is no need to bandpass filter the data. From this figure, we can also see the effect of digitizing a data stream, in that the spectrum repeats at integer multiples of the sampling frequency. Hence the signal is situated at 0+10.7~MHz and 80-10.7~MHz, which is what one would expect from digitizing a 10.7 MHz signal at a sampling rate of 80 MHz. Note that frequency components at 0-10.7~MHz and 80+10.7~MHz are not shown.
%\\ %insert a vertical space before the image
\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.9}{\includegraphics{./figures/fft_sampled_data}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/fft_sampled_data}
\caption{Spectrum of the Sampled IF Data} \label{fig:fft_sampled_data}
\end{center}
\end{figure}

Instead, the data is passed directly on to the demodulator circuitry which  attempts to undo the operations performed by the modulator in order to recover the transmitted signal. To achieve this goal, the data stream is split into two nearly identical paths -- one for the inphase portion of the signal and another for the quadrature portion. Then, the inphase stream is multiplied by a cosine wave which is matched to the carrier frequency of 10.7~MHz, while the quadrature data stream is multiplied by a sine wave of the same frequency. Based on the well known trigonometric identities, 
\begin{eqnarray*}
\cos{A}\cos{B}=\frac{1}{2}\left[\cos{(A+B)}+\cos{(A-B)}\right]\\
\sin{A}\sin{B}=\frac{1}{2}\left[\sin{(A+B)}+\sin{(A-B)}\right],
\end{eqnarray*}

\noindent and noting that the frequencies A and B are identical between the modulator and the demodulator, we are left with the spectrum located at the sum and difference frequencies. In this case, the sum frequency is 21.4~MHz and the difference is 0~MHz, or baseband, as shown for the inphase channel in \autoref{fig:fft_mixed_i_data}. The same situation applies for the quadrature data.
%\\ %insert a vertical space before the image
%\begin{figure}[!htbp]
%\clearpage
\begin{figure}[!p]
\begin{center}
%\scalebox{0.9}{\includegraphics{./figures/fft_mixed_i_data}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/fft_mixed_i_data}
\caption{Spectrum of Mixed Inphase Data} \label{fig:fft_mixed_i_data}
\end{center}
\end{figure}

Now that the signals have been moved back to baseband, the double frequency component at 21.4~MHz must be removed. This is accomplished in the FPGA using a single stage digital down conversion architecture. First the signal is low pass filtered to remove the unwanted double frequency components from the spectrum. Then, the signal is downsampled, or decimated, by a factor of four in order to reduce the data rate, and thus the processing requirements for the remainder of the hardware. Note that in order to satisfy Nyquist's criterion in the passband it is necessary to sample the data above 31.4~MHz. However, now that the signal has been returned to baseband, it only occupies 5 MHz bandwidth. By decimating the signal, the sampling frequency is effectively being changed from $F_{s}$ to $F_{s}/N$, where $N$ is the decimation factor. In this case, the new sampling frequency after decimation is 20~MHz, more than enough to fully represent the 5~MHz baseband bandwidth, while reducing the processing speed of the remainder of the hardware by 75\%. However, by decimating the signal, the spectrum is essentially being compressed inward. As such, it is very important to ensure that there are no unwanted signals outside the baseband region before downsampling is performed -- this is why we low pass filter first. Otherwise, the higher frequency components will end up folding back into the signal of interest~\cite{Mu04}. \autoref{fig:fft_lpf_downsampled} depicts the spectrum of the inphase signal after low pass filtering and decimation by four. From this figure, the output SNR of the implemented demodulator circuit can be estimated to be approximately 38.33 dB.
%\\ %insert a vertical space before the image
\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.9}{\includegraphics{./figures/fft_lpf_downsampled}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/fft_lpf_downsampled}
\caption{Spectrum of Digital Down Converted Inphase Signal} \label{fig:fft_lpf_downsampled}
\end{center}
\end{figure}

At this point, a simple linear decision making block is inserted in each of the data paths in order to decide whether the incoming bit is a one or a zero. Using the digitized inphase and quadrature streams the next step would be to add a symbol mapper which would return the inphase and quadrature streams back to raw data. This however, was not done in this case because the data is only comprised of square waves. \autoref{fig:DemodulatorDesign} illustrates the demodulator design for this thesis. Note that this hardware has to be repeated once per incoming IF signal, a total of four times. Furthermore, it should be noted that the inphase and quadrature sides of the demodulator must be identical in order to preserve the phase relationship between the two data streams.
\\ %insert a vertical space before the image
\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.575}{\includegraphics{./figures/DemodulatorDesign}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/DemodulatorDesign}
\caption{Implemented Demodulator Architecture} \label{fig:DemodulatorDesign}
\end{center}
\end{figure}

Unfortunately, the recovery of the content of the inphase and quadrature bit streams is very much reliant on matching the exact frequency and phase of the modulated data. \autoref{fig:DemodConstellation} shows the demodulated constellation output from the FPGA. Note that the final source code (\quartusReg~II project) for the hardware baseband implementation can be found on the enclosed CD-ROM along with several other versions which represent various stages of development and debugging.

\begin{figure}[!htbp]
\begin{center}
%\rotatebox{90}{\scalebox{0.50}{\includegraphics{./figures/DemodConstellation}}}
\rotatebox{90}{\scalebox{0.9}{\includegraphics[width=\textheight,keepaspectratio]{./figures/DemodConstellation}}}
\caption{Demodulated I and Q Constellation} \label{fig:DemodConstellation}
\end{center}
\end{figure}

From this output it can clearly be seen that there is a phase difference between the modulator and the demodulator which is causing the constellation to be rotated slightly. However, it also demonstrates that the system is completely frequency locked since the constellation is not rotating. To determine what the phase difference is between the modulator and demodulator, a \matlabReg script was written which gradually increments a phase offset onto the demodulator output signal; see \autoref{appendix:SimCode} for code. Using this tool, the phase difference was found to be approximately 122.4~degrees. \autoref{fig:RotatedDemodConstellation} shows the result of adding the 122.4~degree offset to the demodulator LO sinusoids. Note that the constellation is now upright, and the inphase and quadrature bit streams are now clearly visible -- I~=~100~kHz and Q~=~250~kHz square waves.

\begin{figure}[!htbp]
\begin{center}
%\rotatebox{90}{\scalebox{0.5}{\includegraphics{./figures/RotatedDemodConstellation}}}
\rotatebox{90}{\scalebox{0.75}{\includegraphics[height=\textwidth,keepaspectratio]{./figures/RotatedDemodConstellation}}}
\caption{Demodulated I and Q Constellation with Phase Corrected} \label{fig:RotatedDemodConstellation}
\end{center}
\end{figure}

\subsection{Carrier Recovery}

For the reason discussed above, most if not all real-world demodulators use a carrier recovery loop which is responsible for extracting the carrier frequency and phase, then using that information to drive the demodulator sinusoids. In so doing, the demodulator tries to get an exact copy of the modulator LO signal in order to achieve proper demodulation. A \matlabReg simulation of the QAM synchronizer circuit described in~\cite{proakisDigiComm}, shown below in \autoref{fig:QAM_Synchronizer}, has been implemented (see \autoref{appendix:SimCode} for code).

\begin{figure}[!htbp]
\begin{center}
%\scalebox{1}{\includegraphics{./figures/QAM_Synchronizer}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/QAM_Synchronizer}
\caption{QAM Synchronizer Circuit \cite{proakisDigiComm}} \label{fig:QAM_Synchronizer}
\end{center}
\end{figure}

The output of the \matlabReg simulation of the synchronizer circuit is shown in \autoref{fig:RecoveredCarrier}. The square law devices are simply squaring multipliers, and the FIR filters were simulated using 256~taps and a 2~kHz passband bandwidth. Furthermore, for this system, $1/(2T)$ = 10.7~MHz and $1/T$ = 21.4~MHz. From the simulation results, one can clearly see the 10.7~MHz carrier signal component. Using this circuit to recover the modulator LO frequency and phase, the recovered sinusoid can then be used to demodulate the inphase and quadrature data streams. 

\begin{figure}[!htbp]
\begin{center}
%\rotatebox{90}{\scalebox{0.5}{\includegraphics{./figures/RecoveredCarrier}}}
\rotatebox{90}{\scalebox{0.75}{\includegraphics[height=\textwidth,keepaspectratio]{./figures/RecoveredCarrier}}}
\caption{\matlabReg Simulation Results for Carrier Recovery Loop} \label{fig:RecoveredCarrier}
\end{center}
\end{figure}

Another possibility is to continue to use the NCO and simply calculate the phase error between its output and the recovered carrier. The resulting error could then be used to update the NCO phase modulation input. Note that a constant value to the phase increment input of the \alteraReg NCO megacore function produces a constant phase offset between 0 and 2$\pi$ according to the relationship defined in \autoref{eqn:AlteraNCOPhaseOffset}. As well, the phase increment input is unsigned binary whereas the cosine and sine outputs are signed binary. Note that none of these details regarding the NCO inputs and outputs are documented in the \alteraReg documentation; they were elicited through various communications with \alteraReg technical support staff~\cite{alteraTechSupportPrivComm}. The number of bits of resolution for the phase modulation input is $N_{bits}$, $\phi_{pm}$ is the desired phase offset in radians, and $N$ is the required input to the phase modulation port in order to achieve this offset,

\begin{equation} \label{eqn:AlteraNCOPhaseOffset}
\phi_{pm} = \frac{2 \pi N}{2^{N_{bits}}}.
\end{equation}

\subsection{LMS Adaptive Filtering}

Aside from the obvious phase offset in the recovered signal, there is also some distortion and warping of the constellation. This is due to non-linearities in the system and the channel itself. In order to compensate for these non-linearities, the most common approach is to implement some form of equalizer circuit which effectively tries to invert the channels' frequency response.

In the case of this system, a 4x4 array of LMS filters was designed not only to overcome radio channel irregularities but also to isolate and recover each individual user's transmitted signals. This is accomplished by first training the filters using a predetermined data stream for each user. As the data stream is transmitted, the error signal, $e_{n}$, is calculated based on the received signal and the known transmitted data. During this training process, the filter taps are updated based on the error and the adaptation constant, $\mu$, as shown in Equations \ref{eqn:LMSAdaptiveFilter1},~\ref{eqn:LMSAdaptiveFilter2}, and~\ref{eqn:LMSAdaptiveFilter3} \cite{haykinAdaptiveFilterTheory},
\begin{equation} \label{eqn:LMSAdaptiveFilter1}
\underline{W_{n+1}}=\underline{W_{n}}+\mu e_{n} \underline{r_{n}}
\end{equation}
\begin{equation} \label{eqn:LMSAdaptiveFilter2}
e_{n} = d_{n} - \hat{d_{n}}
\end{equation}
\begin{equation} \label{eqn:LMSAdaptiveFilter3}
r_{n} = d_{n} + \eta_{n}.
\end{equation}

\autoref{fig:LMS_4x4_filter_sim} shows the simulation output for the adaptive filter array. Based on this output, it is clear that the filter is stabilizing using the 1024-bit training sequence. The \matlabReg source code for the simulation can be found in \autoref{appendix:SimCode}. This filter design will have to be implemented in the future in order to differentiate between the users in the system and minimize any non-linearities in the system and/or channel. However, this simulation is an excellent starting block for physically implementing the filtering design in hardware.

\begin{figure}[!htbp]
\begin{center}
%\rotatebox{90}{\scalebox{0.525}{\includegraphics{./figures/LMS_4x4_filter_sim}}}
\rotatebox{90}{\scalebox{0.75}{\includegraphics[height=\textwidth,keepaspectratio]{./figures/LMS_4x4_filter_sim}}}
\caption{\matlabReg Simulation Results for LMS Adaptive Filter Array} \label{fig:LMS_4x4_filter_sim}
\end{center}
\end{figure}

\section{Centralized Control}

The centralized control algorithm is mainly an application specific task. However, this design provides the underlying infrastructure in terms of cabling and interfacing all the RS-232 devices in the system.

\subsection{\texorpdfstring{\blackBoxRegX}{Black Box\textregistered} RS-232 Control}

The \blackBoxReg COS is responsible for interconnecting all the COTS devices in the system. The communications settings used for this system are imposed by the RS-232 configuration of the AOR radios, since they are only capable of selecting between data rates of 4800, 9600, and 19200~bps, and cannot change other parameters such as the number of data bits, number of stop bits, or the parity~\cite{aorMan}. The Aeroflex signal generator is capable of changing all of the common RS-232 communication parameters in order to match those used by the AOR radios. \autoref{tbl:serialCommSettings} lists the communications parameters which are required to be used for the system. This information does not appear in the AOR Radio manual, it can be found on the last page of the AR5000 RS-232C Command List manual.  
\\ %insert a vertical space before the table
\begin{table}[!htbp]
\begin{center}
\caption{RS-232 Communication Parameters \cite{aorRS232Man}} \label{tbl:serialCommSettings}
\begin{tabular}{|c|c|}
\hline
Parameter& Value\\
\hline
\hline
Data rate& 9600 bps\\
\hline
Data bits& 8\\
\hline
Stop bits& 2\\
\hline
Parity& None\\
\hline
Flow Control& Xon\\
\hline
\end{tabular}
\end{center}
\end{table}

Based on these settings, the \blackBoxReg COS was configured for each of the devices. The radios act as data terminal equipment (DTE), the signal generator acts as data communications equipment (DCE), and the FPGA has been selected to act as a DTE. The DIP switch settings which were established to internally configure the COS to meet the communication requirements of the system devices are listed in \autoref{appendix:SystemSpecs}. The remainder of the details for configuring the system are specific to the test scenario being developed, and thus are left up to the developer. Note that all the RS-232 cables created for interconnecting the hardware are straight though cables, not null modems. Any switching between DTE and DCE is done using the \blackBoxReg COS.

\section{System Configuration}

A complete description of the cabling used in this design is provided in \autoref{appendix:SystemSpecs}. A list of all cables created for this design as well as information on how the system should be interconnected for use in a 1x1 or 4x4 configuration can be found there. \autoref{appendix:SystemSpecs} also contains a section describing the proper configuration of the COTS hardware to achieve correct system operation.
