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\chapter{Summary and Future Work} \label{chap:Summary}
\section{Summary of Work Completed}

This thesis provides the design and implementation of the physical layer hardware for a reconfigurable MIMO SDR based wireless testbed. The design incorporates the concept of SWAP gain as well as diversity gain, and is designed for use in investigating radio channel properties as well as the implementation of algorithms in a real-world environment. The design process along with the implementation details of each subcomponent is presented in detail.

A simple quadrature demodulator design was created within the FPGA and used to verify the correct operation of the system. A \matlabReg simulation of an adaptive LMS filter array for channel equalization and recovery of user signals was developed. As well, a carrier recovery loop was developed and simulated in \matlabRegNS. Both components exhibit the desired functionality and are ready for future implementation.

The overall testbed system design has been completed, the hardware has been either designed and built or selected and obtained, and the necessary interfacing hardware and software has been developed. The system is now ready for the remaining components to be added, after which it will be ready for use in taking field measurements for characterization of the radio channel.

\section{Future Work}

Due to the large size of this system, and the various stages of debugging that were required, some issues were discovered late which require additional hardware to be purchased or built before the system implementation is 100\% complete. In terms of new hardware, the following items are required: eight power supplies, or long power cables, to power the remote transmitters and receivers, four 50~$\Omega$ feed-through terminators for the 10~MHz clock lines to the radios, and a variable amplifier or fixed amplifier with variable attenuator for driving the 10~MHz clock lines to the radios. The only components left to build are three more bias circuits for the Hittite modulators. These boards are very simple, and should be a direct reproduction of the existing board, thus no design is required.

Future FPGA development work includes implementing the LMS adaptive filter array as well as the carrier recovery circuit in hardware. As well, the implementation of an RS-232 transmitter would be required in order to provide RS-232 control of the system components. The RS-232 transmitter should be simple to create as a parallel load shift register operating at 9600~bps. From that point, the underlying testbed system would be complete, and a user could develop their own test modules on top of the design. Finally, before any real-world testing can be performed with the system radiating in the 2.4~GHz ISM band, there is a need to investigate and meet any requirements or limitations imposed by RSS-210~\cite{rss210}.
