%%---------------Appendices--------------------------------
\phantomsection\addcontentsline{toc}{chapter}{Appendices}
\appendix
\chapter{System Specifications} \label{appendix:SystemSpecs}

\section{\texorpdfstring{\alteraRegX}{Altera\textregistered} Pinouts to AD6645 ADC Boards}

The pinouts provided in both the \alteraReg and Analog Devices documentation for the external AD6645 ADC connections to \alteraReg FPGA interface connector are not correct. Tables~\ref{tbl:ADCPinoutsJ5} and~\ref{tbl:ADCPinoutsJ6} provide the correct interconnection information.

\begin{table}[!htbp]
\begin{center}
\caption{ADC Board to \alteraReg FPGA Board Connector J5 Pinout \cite{Ch35}} \label{tbl:ADCPinoutsJ5}
\begin{tabular}{|c|c||c|c|c|c|}
\hline
%\multicolumn{2}{|c|}{Generating Polynomials}\\
%\hline
\multicolumn{2}{|c||}{AD6645 ADC Board} &
\multicolumn{4}{c|}{\stratixReg II FPGA Development Board}\\
\hline
Pin Number& Signal& Connector& Pin Number& Signal& \stratixReg II Pin\\
\hline
\hline
33& B13& J5& 33& adi\_D15& P2\\
\hline
31& B12& J5& 31& adi\_D14& P1\\
\hline
29& B11& J5& 29& adi\_D13& R3\\
\hline
27& B10& J5& 27& adi\_D12& R2\\
\hline
25& B9& J5& 25& adi\_D11& M2\\
\hline
23& B8& J5& 23& adi\_D10& M1\\
\hline
21& B7& J5& 21& adi\_D9& N3\\
\hline
19& B6& J5& 19& adi\_D8& N2\\
\hline
17& B5& J5& 17& adi\_D7& L2\\
\hline
15& B4& J5& 15& adi\_D6& L1\\
\hline
13& B3& J5& 13& adi\_D5& M4\\
\hline
11& B2& J5& 11& adi\_D4& M3\\
\hline
9& B1& J5& 9& adi\_D3& N5\\
\hline
7& B0& J5& 7& adi\_D2& N4\\
\hline
5& GND& J5& 5& adi\_D1& L4\\
\hline
3& GND& J5& 3& adi\_D0& L3\\
\hline
\end{tabular}
\end{center}
\end{table}

\begin{table}[!htbp]
\begin{center}
\caption{ADC Board to \alteraReg FPGA Board Connector J6 Pinout \cite{Ch35}} \label{tbl:ADCPinoutsJ6}
\begin{tabular}{|c|c||c|c|c|c|}
\hline
%\multicolumn{2}{|c|}{Generating Polynomials}\\
%\hline
\multicolumn{2}{|c||}{AD6645 ADC Board} &
\multicolumn{4}{c|}{\stratixReg II FPGA Development Board}\\
\hline
Pin Number& Signal& Connector& Pin Number& Signal& \stratixReg II Pin\\
\hline
\hline
33& B13& J6& 33& adi\_D32& M8\\
\hline
31& B12& J6& 31& adi\_D31& M11\\
\hline
29& B11& J6& 29& adi\_D30& M10\\
\hline
27& B10& J6& 27& adi\_D29& L6\\
\hline
25& B9& J6& 25& adi\_D28& L5\\
\hline
23& B8& J6& 23& adi\_D27& K7\\
\hline
21& B7& J6& 21& adi\_D26& K6\\
\hline
19& B6& J6& 19& adi\_D25& L8\\
\hline
17& B5& J6& 17& adi\_D24& L7\\
\hline
15& B4& J6& 15& adi\_D23& L10\\
\hline
13& B3& J6& 13& adi\_D22& L9\\
\hline
11& B2& J6& 11& adi\_D21& K9\\
\hline
9& B1& J6& 9& adi\_D20& K8\\
\hline
7& B0& J6& 7& adi\_D19& J9\\
\hline
5& GND& J6& 5& adi\_D18& J8\\
\hline
3& GND& J6& 3& adi\_D17& J7\\
\hline
\end{tabular}
\end{center}
\end{table}

\section{Cabling and System Interconnections} \label{sec:Cabling}

Two types of cabling were used for the development of this system, one coaxial and the other RS-232 cable. Due to the large antenna separations in this system, the choice of cabling was made in order to minimize attenuation. The RS-232 cabling chosen was Belden model~1422A, a stranded five pair low capacitance computer cable for RS-232. This cable, coupled with a low data rate of 9600~baud, was found to support transmission of RS-232 signals at distances of at least 300~feet. The coaxial cable chosen was Belden model~9201, an RG-58/U type cable with a nominal attenuation of 1.1~dB per 100~feet at a frequency of 10~MHz~\cite{belden9201Man}. A slight trade-off was made with the choice of the coaxial cable - the characteristic impedance of Belden~9201 is 51.5~$\Omega$. In an effort to reduce cost, more than \$1000, a similar cable with a characteristic impedance of 50~$\Omega$ was overlooked. In exchange for the reduction in cost, the voltage reflection coefficient, $\Gamma$ becomes non-zero as shown in \autoref{eqn:VoltageReflectionCoeff},

\begin{equation} \label{eqn:VoltageReflectionCoeff}
\Gamma = \frac{Z_{L} - Z_{0}}{Z_{L} + Z_{0}} = \frac{50-51.5}{50+51.5} = -0.0148 ~~\cite{chengFieldsAndWaves}.\\
\end{equation}

Using the reflection coefficient, the voltage standing-wave ratio (VSWR) can be calculated as,

\begin{equation} \label{eqn:VoltageStandingWaveRatio}
\mathrm{VSWR} = \frac{1+\left|\Gamma\right|}{1-\left|\Gamma\right|} = \frac{1+0.0148}{1-0.0148} = 1.03 ~~\cite{chengFieldsAndWaves}.\\
\end{equation}

From this result it is clear that the cable to load impedance mismatch is negligible in this case.

To further minimize cost, the cabling was purchased in spools of 500 and 1000 feet. The cables were then cut to length and connectorized using SMA, BNC, and N-Type connectors as required in order to avoid having to purchase converters as well as to avoid any additional attenuation in the converters. After each cable was made, it was tested for both continuity and length using a time domain reflectometer. A similar procedure was performed for the RS-232 cables, where each cable was provided either a DB9 or DB25 connector as necessary, and tested using Hyperterminal. \autoref{tbl:CableInventory} provides a cable inventory of all cables created for the testbed. Note that the cable label column corresponds to the labels attached to the cable.

\begin{table}[!htbp]
\begin{center}
\caption{Testbed Cable Inventory} \label{tbl:CableInventory}
\begin{tabular*}{\textwidth}%[t]
{@{\extracolsep{\fill}}|p{1.5cm}|p{1.3cm}|p{0.625cm}|p{1.25cm}|p{3cm}|p{3.5cm}|}
\hline
Cable Label& Cable Type& Qty& Length (ft)& Connectors& Purpose\\
\hline
\hline
IQ1-IQ8& Coaxial& 8& 300& SMA, SMA& I and Q signals from FPGA (PCB) to Hittite\\
\hline
RF2-5& Coaxial& 4& 300& SMA, SMA& Sig. Gen. to Hittite\\
\hline
IF1-4& Coaxial& 4& 300& SMA, BNC& AOR IF to ADC\\
\hline
STD4-7& Coaxial& 4& 300& BNC, BNC& 10 MHz std. to AOR\\
\hline
TX1-4& Coaxial& 4& 8& SMA, N-Type& Hittite to $T_{x}$ ant.\\
\hline
RX1-4& Coaxial& 4& 8& N-Type, N-Type& $R_{x}$ ant. to radio\\
\hline
STD2& Coaxial& 1& 3& SMA, BNC& 10 MHz std. to clk PCB\\
\hline
STD3& Coaxial& 1& 2& SMA, SMA& Clk PCB to FPGA\\
\hline
STD1& Coaxial& 1& 2& BNC, BNC& 10 MHz std. to BNC splitter\\
\hline
RF1& Coaxial& 1& 2& N-Type, SMA& Aeroflex to SMA power divider\\
\hline
ENC1-4& Coaxial& 4& 2& SMA, SMA& FPGA (PCB) Encode to ADC\\
\hline
GP1& Coaxial& 1& 3& SMA, BNC& General purpose\\
\hline
GP2-5& Coaxial& 4& 4& SMA, SMA& General purpose\\
\hline
GP6-8& Coaxial& 3& 4& BNC, BNC& General purpose\\
\hline
HIT1-3& Coaxial& 3& 2& SMA, SMA& Hittite bias PCB to Hittite\\
\hline
CON1& RS-232& 1& 10& DB9 M, DB25 M& COS to FPGA\\
\hline
CON2& RS-232& 1& 10& DB9 F, DB25 M& COS to Aeroflex\\
\hline
CON3-6& RS-232& 4& 300& DB9 M, DB25 M& COS to AOR\\
\hline
\multicolumn{6}{|c|}{Total number of cables: 53}\\
\hline
%\end{tabular}
\end{tabular*}
\end{center}
\end{table}

In the future, in order to connect the three additional Hittite bias PCB boards, nine more three foot coaxial cables will have to be made. As mentioned previously, the RS-232 cables are all wired straight through. \autoref{tbl:RS232Wiring} details the wiring of the RS-232 cables.

\begin{table}[!htbp]
\begin{center}
\caption{RS-232 Connector Wiring} \label{tbl:RS232Wiring}
\begin{tabular}{|c|c|c|c|}
\hline
%\multicolumn{2}{|c|}{Generating Polynomials}\\
%\hline
Wire Colour& DB9 Connector& DB25 Connector& Signal\\
\hline
\hline
Blue& 1& 8& DCD\\
\hline
White/Orange& 2& 3& $\mathrm{R_{x}}$\\
\hline
Orange& 3& 2& $\mathrm{T_{x}}$\\
\hline
White/Blue& 4& 20& DTR\\
\hline
Green& 5& 7& GND\\
\hline
White/Brown& 6& 6& DSR\\
\hline
Green/White& 7& 4& RTS\\
\hline
Brown& 8& 5& CTS\\
\hline
Grey& 9& 22& RI\\
\hline
White/Grey& NC& NC& -\\
\hline
\end{tabular}
\end{center}
\end{table}

\section{\texorpdfstring{\blackBoxRegX}{Black Box\textregistered} COS Configuration}

The DIP switch postions required for the RS-232 configuration used in this design are as provided in \autoref{tbl:DIPSwitchPositions}, where C denotes a closed switch, and O denotes an open switch. Note that each port of the switch must operate in the opposite mode of whatever device is connected. For example, since the FPGA acts as a DTE, the port on the COS to which it is connected must act as a DCE. Detailed information regarding the meaning of these settings can be found in the device manual, see~\cite{BlackBoxMan}.

\begin{table}[!htbp]
\begin{center}
\caption{COS DIP Switch Positions} \label{tbl:DIPSwitchPositions}
\begin{tabular}{|c|c|c|c|}
\hline
%\multicolumn{2}{|c|}{Generating Polynomials}\\
%\hline
Switch& Device & COS Port Config. & Value\\
\hline
\hline
\multirow{2}{*}{SW1} & \multirow{2}{*}{FPGA} & \multirow{2}{*}{DCE} & A: OOOOOCCO\\ &&& B: COOCCCCC\\
\hline
\multirow{2}{*}{SW2} & \multirow{2}{*}{Signal Gen.} & \multirow{2}{*}{DTE} & A: OOOOCOOC\\ &&& B: OCCOCCCC\\
\hline
\multirow{2}{*}{SW3} & \multirow{2}{*}{Radio} & \multirow{2}{*}{DCE} & A: OOOOOCCO\\ &&& B: COOCCCCC\\
\hline
\multirow{2}{*}{SW4} & \multirow{2}{*}{Radio} & \multirow{2}{*}{DCE} & A: OOOOOCCO\\ &&& B: COOCCCCC\\
\hline
\multirow{2}{*}{SW5} & \multirow{2}{*}{Radio} & \multirow{2}{*}{DCE} & A: OOOOOCCO\\ &&& B: COOCCCCC\\
\hline
SW6& COS Internal Setting & N/A & OCCOOOCO\\
\hline
SW7& COS Internal Setting & N/A & COOCOOOO\\
\hline
SW8& COS Internal Setting & N/A & CCOCCCCC\\
\hline
SW9& COS Internal Setting & N/A & COOO\\
\hline
SW10& COS Internal Setting & N/A & OOOOCOOO\\
\hline
\multirow{2}{*}{SW11} & \multirow{2}{*}{Radio} & \multirow{2}{*}{DCE} & A: OOOOOCCO\\ &&& B: COOCCCCC\\
\hline
\multirow{2}{*}{SW12} & \multirow{2}{*}{Unused} & \multirow{2}{*}{N/A} & A: XXXXXXXX\\ &&& B: XXXXXXXX\\
\hline
\multirow{2}{*}{SW13} & \multirow{2}{*}{Unused} & \multirow{2}{*}{N/A} & A: XXXXXXXX\\ &&& B: XXXXXXXX\\
\hline
\multirow{2}{*}{SW14} & \multirow{2}{*}{Unused} & \multirow{2}{*}{N/A} & A: XXXXXXXX\\ &&& B: XXXXXXXX\\
\hline
\end{tabular}
\end{center}
\end{table}

\section{System Test Setup}

The design and development of this system was performed with the following settings for the radios and signal generator. The signal generator frequency was set to 2.45~GHz, approximately the middle of the ISM band, with a gain of 0~dBm and all modulation disabled. The radios were also tuned to 2.45~GHz, with the AGC enabled.

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\chapter{\texorpdfstring{\matlabRegX}{MATLAB\textregistered} Simulation and Debugging Source Code} \label{appendix:SimCode}

\section{LMS Adaptive Filter Array}
\scriptsize
\begin{verbatim}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% JAH_LMS  This implements an 4x4 array of LMS filters of the specified order.
%
% Author: J. Andy Harriman    SN: 3020639    Course: EE 6997
% Date: Feb 27, 2006
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

clear;
clear functions;
clf;

numBits = 2^10; % The number of bits to transmit
filterOrder = 6; % The order of the filters
variance = 10^(-3); % The variance of the noise
stdDev = sqrt(variance); % The standard deviation of the noise
delay = 1; % decoding delay
sampling_phase = -4;  % fractional phase at the sampler
mu = 2^(-6); % LMS adaptation constant
k = 4; %upsampling factor

dn_upsampled1 = zeros(1,numBits*k);
dn_upsampled2 = zeros(1,numBits*k);
dn_upsampled3 = zeros(1,numBits*k);
dn_upsampled4 = zeros(1,numBits*k);

% Generate the random data to transmit
% Note that the data transmitted is a uniformly distributed discrete RV
dn1 = 2*(rand(1,numBits)<0.5)-1; 
dn2 = 2*(rand(1,numBits)<0.5)-1; 
dn3 = 2*(rand(1,numBits)<0.5)-1; 
dn4 = 2*(rand(1,numBits)<0.5)-1; 

%upsample the data to be transmitted by k
dn_upsampled1(1) = dn1(1);
for i = 1 : numBits-1,
    dn_upsampled1((i*k)+1) = dn1(i+1);
end
dn_upsampled2(1) = dn2(1);
for i = 1 : numBits-1,
    dn_upsampled2((i*k)+1) = dn2(i+1);
end
dn_upsampled3(1) = dn3(1);
for i = 1 : numBits-1,
    dn_upsampled3((i*k)+1) = dn3(i+1);
end
dn_upsampled4(1) = dn4(1);
for i = 1 : numBits-1,
    dn_upsampled4((i*k)+1) = dn4(i+1);
end

% generate random 4-tap fir filters the 16 radio channels
channel11 = 2*rand(1,4)-1;
channel12 = 2*rand(1,4)-1;
channel13 = 2*rand(1,4)-1;
channel14 = 2*rand(1,4)-1;
channel21 = 2*rand(1,4)-1;
channel22 = 2*rand(1,4)-1;
channel23 = 2*rand(1,4)-1;
channel24 = 2*rand(1,4)-1;
channel31 = 2*rand(1,4)-1;
channel32 = 2*rand(1,4)-1;
channel33 = 2*rand(1,4)-1;
channel34 = 2*rand(1,4)-1;
channel41 = 2*rand(1,4)-1;
channel42 = 2*rand(1,4)-1;
channel43 = 2*rand(1,4)-1;
channel44 = 2*rand(1,4)-1;

bp_test_flag_1 = 1
if ( bp_test_flag_1 == 1 ) ,
    channel11 = 2*rand(1,4)-1;
    channel12 = 0*rand(1,4)-0;
    channel13 = 0*rand(1,4)-0;
    channel14 = 0*rand(1,4)-0;
    channel21 = 0*rand(1,4)-0;
    channel22 = 2*rand(1,4)-1;
    channel23 = 0*rand(1,4)-0;
    channel24 = 0*rand(1,4)-0;
    channel31 = 0*rand(1,4)-0;
    channel32 = 0*rand(1,4)-0;
    channel33 = 2*rand(1,4)-1;
    channel34 = 0*rand(1,4)-0;
    channel41 = 0*rand(1,4)-0;
    channel42 = 0*rand(1,4)-0;
    channel43 = 0*rand(1,4)-0;
    channel44 = 2*rand(1,4)-1;
end

%Pass the data generated at each transmitter through each of its associated
%paths to the receivers. Each transmitted signal will be received by each
%receiver, therefore we have 4x4=16 radio channels.

rx11 = zeros(1,numBits*k);
rx12 = zeros(1,numBits*k);
rx13 = zeros(1,numBits*k);
rx14 = zeros(1,numBits*k);
rx21 = zeros(1,numBits*k);
rx22 = zeros(1,numBits*k);
rx23 = zeros(1,numBits*k);
rx24 = zeros(1,numBits*k);
rx31 = zeros(1,numBits*k);
rx32 = zeros(1,numBits*k);
rx33 = zeros(1,numBits*k);
rx34 = zeros(1,numBits*k);
rx41 = zeros(1,numBits*k);
rx42 = zeros(1,numBits*k);
rx43 = zeros(1,numBits*k);
rx44 = zeros(1,numBits*k);

%4 paths for transmitter 1
rx11 = jah_fir_filter(dn_upsampled1,channel11);
rx12 = jah_fir_filter(dn_upsampled1,channel12);
rx13 = jah_fir_filter(dn_upsampled1,channel13);
rx14 = jah_fir_filter(dn_upsampled1,channel14);
%4 paths for transmitter 2
rx21 = jah_fir_filter(dn_upsampled2,channel21);
rx22 = jah_fir_filter(dn_upsampled2,channel22);
rx23 = jah_fir_filter(dn_upsampled2,channel23);
rx24 = jah_fir_filter(dn_upsampled2,channel24);
%4 paths for transmitter 3
rx31 = jah_fir_filter(dn_upsampled3,channel31);
rx32 = jah_fir_filter(dn_upsampled3,channel32);
rx33 = jah_fir_filter(dn_upsampled3,channel33);
rx34 = jah_fir_filter(dn_upsampled3,channel34);
%4 paths for transmitter 4
rx41 = jah_fir_filter(dn_upsampled4,channel41);
rx42 = jah_fir_filter(dn_upsampled4,channel42);
rx43 = jah_fir_filter(dn_upsampled4,channel43);
rx44 = jah_fir_filter(dn_upsampled4,channel44);

% model the thermal noise at input to each receiver
thermal_noise1 = stdDev*randn(1,numBits*k);
thermal_noise2 = stdDev*randn(1,numBits*k);
thermal_noise3 = stdDev*randn(1,numBits*k);
thermal_noise4 = stdDev*randn(1,numBits*k);

% The received data at each receiver is the sum of each of the 4
% transmitted values which have passed through different channels...
rn1 = rx11 + rx21 + rx31 + rx41 + thermal_noise1;
rn2 = rx12 + rx22 + rx32 + rx42 + thermal_noise2;
rn3 = rx13 + rx23 + rx33 + rx43 + thermal_noise3;
rn4 = rx14 + rx24 + rx34 + rx44 + thermal_noise4;

w1 = zeros(1,filterOrder);
w2 = zeros(1,filterOrder);
w3 = zeros(1,filterOrder);
w4 = zeros(1,filterOrder);

error_log1 = zeros(1,numBits);
error_log2 = zeros(1,numBits);
error_log3 = zeros(1,numBits);
error_log4 = zeros(1,numBits);

delay = 0;
sampling_phase = 0;

%run simulation for receiver 1
for i = 1 : numBits*k,
    if(i-(filterOrder-1)+sampling_phase>=1 & i-(0-1)+sampling_phase <= length(rn1) &
    	(i-1)/k-delay >= 1),
        if(mod(i-1,k) == 0),
            dn_hat = 0;
            for j = 1 : filterOrder,
                dn_hat = dn_hat + w1(j) * rn1(i-(j-1)+sampling_phase);
            end

            error = dn1((i-1)/k-delay) - dn_hat;

            error_log1((i-1)/k) = error;

            %adjust the tap coefficients
            for j = 1 : filterOrder,
                w1(j) = w1(j) + mu * error * rn1(i-(j-1)+sampling_phase);
            end    
        end
    end
end
wAxisCoordinates = [0:length(w1)-1];

%receiver 1
figure(1);
subplot(241);
stem(wAxisCoordinates, abs(w1).^2, 'o');
ylabel('|w|^2');
xlabel('Index, i, (-)');

subplot(245);
se_db = 10 * log10(abs(error_log1)+eps);
plot(se_db)
axis([0 (numBits-1) -40 10]);

%run simulation for receiver 2
count = 0 ;
count2=1;
for i = 1 : numBits*k,
    if ( 1 <= (i-delay) & ((i-(filterOrder-1))>0)),
       
        dn_hat = 0;
        for j = 1 : filterOrder,
            dn_hat = dn_hat + w2(j) * rn2(i-(j-1));
        end

        count=count+1;
        %only need to calculate error and update w every 4 samples
        if(count==k),
            error = dn_upsampled2(i-delay*k) - dn_hat;
            %error_log(i-delay) = error;
            error_log2(count2) = error;
            
            %adjust the tap coefficients
            for j = 1 : filterOrder,
                w2(j) = w2(j) + mu * error * rn2(i-(j-1));
            end
            count = 0;
            count2=count2+1;
        end
    end
end

%run simulation for receiver 3
count = 0 ;
count2=1;
for i = 1 : numBits*k,
    if ( 1 <= (i-delay) & ((i-(filterOrder-1))>0)),
       
        dn_hat = 0;
        for j = 1 : filterOrder,
            dn_hat = dn_hat + w3(j) * rn3(i-(j-1));
        end

        count=count+1;
        %only need to calculate error and update w every 4 samples
        if(count==k),
            error = dn_upsampled3(i-delay*k) - dn_hat;
            %error_log(i-delay) = error;
            error_log3(count2) = error;
            
            %adjust the tap coefficients
            for j = 1 : filterOrder,
                w3(j) = w3(j) + mu * error * rn3(i-(j-1));
            end
            count = 0;
            count2=count2+1;
        end
    end
end

%run simulation for receiver 4
count = 0 ;
count2=1;
for i = 1 : numBits*k,
    if ( 1 <= (i-delay) & ((i-(filterOrder-1))>0)),
       
        dn_hat = 0;
        for j = 1 : filterOrder,
            dn_hat = dn_hat + w4(j) * rn4(i-(j-1));
        end

        count=count+1;
        %only need to calculate error and update w every 4 samples
        if(count==k),
            error = dn_upsampled4(i-delay*k) - dn_hat;
            %error_log(i-delay) = error;
            error_log4(count2) = error;
            
            %adjust the tap coefficients
            for j = 1 : filterOrder,
                w4(j) = w4(j) + mu * error * rn4(i-(j-1));
            end
            count = 0;
            count2=count2+1;
        end
    end
end

wAxisCoordinates = [0:length(w1)-1];

%receiver 1
figure(1);
subplot(241);
stem(wAxisCoordinates, abs(w1).^2, 'o');
ylabel('|w|^2');
xlabel('Index, i, (-)');

subplot(245);
se_db = 10 * log10(abs(error_log1)+eps);
plot(se_db)
axis([0 (numBits-1) -40 10]);

%receiver 2
subplot(242);
stem(wAxisCoordinates, abs(w2).^2, 'o');
ylabel('|w|^2');
xlabel('Index, i, (-)');

subplot(246);
se_db = 10 * log10(abs(error_log2)+eps);
plot(se_db)
axis([0 (numBits-1) -40 10]);

%receiver 3
subplot(243);
stem(wAxisCoordinates, abs(w3).^2, 'o');
ylabel('|w|^2');
xlabel('Index, i, (-)');

subplot(247);
se_db = 10 * log10(abs(error_log3)+eps);
plot(se_db)
axis([0 (numBits-1) -40 10]);

%receiver 4
subplot(244);
stem(wAxisCoordinates, abs(w4).^2, 'o');
ylabel('|w|^2');
xlabel('Index, i, (-)');

subplot(248);
se_db = 10 * log10(abs(error_log4)+eps);
plot(se_db)
axis([0 (numBits-1) -40 10]);
\end{verbatim}
\normalsize
\newpage

\section{Constellation Plotter}
\scriptsize
\begin{verbatim}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% JAH_CONSTELLATION_PLOTTER This script plots the demodulated inphase and
% quadrature signals, along with the corresponding 4-QAM constellation, 
% based on the signal stored in data, over the range from 0 to 2*pi.
%
% Author: J. Andy Harriman
% Date: June 26, 2006
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%


%data = xlsread('data36.xls');
%import_data36

fi = 10.7e6;
t = time/10^12;
h2=fir1(64,0.05,'low');

%delta = 0.26; %43.2'

for i=0:0.01:2,
    yc = cos(2*pi*fi*t+i*pi);
    zc = adc_sDec .* (yc');
    zfc = conv(h2,zc);
   
    ys = sin(2*pi*fi*t+i*pi);
    zs = adc_sDec .* (ys');
    zfs = conv(h2,zs);
    
    subplot(311)
    plot(t,zfc(1:length(t)));legend(['i = ' num2str(i) '*pi = ' num2str(i*pi*180/pi) 'deg'])
    subplot(312)
    plot(t,zfs(1:length(t)));legend(['q = ' num2str(i) '*pi = ' num2str(i*pi*180/pi) 'deg'])
    subplot(313)
    plot(zfc,zfs); grid on
        
    if i == 0.68,
         
         %colors: blue = 0, red = 1
        color = 0;
        for j = 1:10,
            if color == 0, %if(blue)
                subplot(311)
                plot(t,zfc(1:length(t)),'r');legend(['i = ' num2str(i) '*pi = '
                		 num2str(i*pi*180/pi) 'deg'])
                subplot(312)
                plot(t,zfs(1:length(t)),'r');legend(['q = ' num2str(i) '*pi = '
                		 num2str(i*pi*180/pi) 'deg'])
                subplot(313)
                plot(zfc,zfs,'r'); grid on
                color = 1; %color = red
                pause(0.5)
            else
                subplot(311)
                plot(t,zfc(1:length(t)),'b');legend(['i = ' num2str(i) '*pi = '
                		 num2str(i*pi*180/pi) 'deg'])
                subplot(312)
                plot(t,zfs(1:length(t)),'b');legend(['q = ' num2str(i) '*pi = '
                		 num2str(i*pi*180/pi) 'deg'])
                subplot(313)
                plot(zfc,zfs,'b'); grid on
                color = 0; %color = blue
                pause(0.5)
            end
            return
        end
    end
    pause(0.05)
    %pause
end
\end{verbatim}
\normalsize
\newpage

\section{QAM Synchronizer}

\scriptsize
\begin{verbatim}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% JAH_QAM_SYNCHRONIZER This script simulates the transmit and receive
% fuctions of a QAM transceiver. The demodulated signal is then used to
% perform carrier recovery.
%
% Author: J. Andy Harriman
% Date: June 26, 2006
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

clear;

nSamples = 4096; %number of samples to take
fs = 80e6; %sampling rate = 80MSPS
samplePeriod = 1/fs;
t = samplePeriod:samplePeriod:(samplePeriod*nSamples); %time in ns
f_if = 10.7e6; %IF frequency

f_i = 100e3; %100 kHz inphase signal
f_q = 250e3; %250 kHz inphase signal
i_in = square(2*pi*f_i*t);
q_in = square(2*pi*f_q*t);
%plot(t,i_in,t,q_in);legend('i input','q input');

%modulator board
%fc = 2.4e9; %2.4 GHz carrier
fc = 10.7e6;
ic = cos(2*pi*fc*t).*i_in;
qs = sin(2*pi*fc*t).*q_in;
y_tx = ic + qs;

%channel
y_rx = y_tx; %assume channel is perfect

%FPGA board
%NCO sine and cosine outputs for demodulation
phi_deg = 0;
phi_rad = phi_deg * pi/180;

yc = cos(2*pi*f_if*t + phi_rad);
ys = sin(2*pi*f_if*t + phi_rad);
%plot(t(1:100),yc(1:100),t(1:100),ys(1:100));legend('cos','sin');

zc = yc .* y_rx;
zs = ys .* y_rx;

%low pass filter the data
nTaps = 64; %64 tap filter
h1=fir1(nTaps,0.0625,'low'); % cutoff = 5 MHz
zfc = conv(h1,zc);
zfs = conv(h1,zs);
%plot(t,zfc(1:length(t)),t,zfs(1:length(t)));legend('i output','q output');
%plot(zfc,zfs);

%downsample by 4
%zfc_ds = decimate(zfc,4);
%zfs_ds = decimate(zfs,4);

%carrier recovery loop
h2 = fir1(512,[0.13374 0.13376],'bandpass'); %10.699-10.7001 MHz
i_sync = conv(h2,zc);
q_sync = conv(h2,zs);

test = conv(h2,zc);
N=length(test);
f = [0:(N-1)]*(fs/N);
%plot(f,abs(fft(test)))
%plot(test)

test=test.^2;
%plot(f,abs(fft(test)))

test2 = conv(h2,zs);
test2 = test2.^2;
%plot(f,abs(fft(test2)))

test3 = test+test2;
%plot(f,abs(fft(test3)))

h3 = fir1(512,[0.26749 0.26751],'bandpass'); %21.399-21.4001 MHz
test4 = conv(h3,test3);

N=length(test4);
f = [0:(N-1)]*(fs/N);
%plot(f,abs(fft(test4)))

subplot(211)
plot(t,test4(1:length(t)))
subplot(212)
plot(f,abs(fft(test4)))
\end{verbatim}
\normalsize
\newpage

\section{\texorpdfstring{\signaltapRegX}{SignalTap\textregistered} to \texorpdfstring{\matlabRegX}{MATLAB\textregistered} Example}

The script provided below demonstrates how to import data from a SignalTap .csv file, with the header information removed, into the \matlabReg workspace. The scripts which are used to perform the binary to decimal conversion are provided in the following section.

\scriptsize
\begin{verbatim}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% JAH_IMPORT_DATA This script extracts the binary data stored in the
% variable 'data', and converts the recovered variables back to decimal.
%
% Author: J. Andy Harriman
% Date: June 26, 2006
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%


%Extract the data from the appropriate cells

time = data(:,1);
adc = data(:,3:16);
nco_sin = data(:,18:31);
nco_cos = data(:,33:46);
lpm_q = data(:,48:75);
lpm_i = data(:,77:104);
lpf_q = data(:,106:144);
lpf_i = data(:,146:184);

%Combine the values consisting of multiple columns (binary) into their decimal equivalent
[adc_sDec,adc_uDec] = jah_sbin2dec(adc);
[nco_sin_sDec,nco_sin_uDec] = jah_sbin2dec(nco_sin);
[nco_cos_sDec,nco_cos_uDec] = jah_sbin2dec(nco_cos);
[lpm_q_sDec,lpm_q_uDec] = jah_sbin2dec(lpm_q);
[lpm_i_sDec,lpm_i_uDec] = jah_sbin2dec(lpm_i);
[lpf_q_sDec,lpf_q_uDec] = jah_sbin2dec(lpf_q);
[lpf_i_sDec,lpf_i_uDec] = jah_sbin2dec(lpf_i);
\end{verbatim}
\normalsize
\newpage

\subsection{Binary-to-Decimal Conversion Scripts}

\scriptsize
\begin{verbatim}
function [signedResult,unsignedResult] = jah_ubin2dec(ubin);
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% JAH_UBIN2DEC  This function returns the decimal equivalent, both a
% signed and an unsigned version, of the unsigned binary NxM array of
% numbers passed in.
%
% Parameters: 
% ubin = the array of unsigned binary values
%
% Author: J. Andy Harriman
% Date: April 27, 2006
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

numBits = length(ubin(1,:));

if(numBits <=1),
    disp('Error: The number of bits must be greater than or equal to 1.')
    result = NaN;
    return
end


k = 1;
for j = 1:1:size(ubin,1),
    signedResult(k) = 0;

    if(ubin(j,1)), %MSB is set
        signedResult(k) = 0-2^(numBits);
    end

    for i = 2:1:numBits,
        signedResult(k) = signedResult(k) + ubin(j,i) * 2^(numBits-i);
    end

    k = k + 1;
end

k = 1;
for j = 1:1:size(ubin,1),
    unsignedResult(k) = 0;

    for i = 1:1:numBits,
        unsignedResult(k) = unsignedResult(k) + ubin(j,i) * 2^(numBits-i);
    end

    k = k + 1;
end
\end{verbatim}
\normalsize
\newpage

\scriptsize
\begin{verbatim}
function [signedResult,unsignedResult] = jah_sbin2dec(sbin);
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% JAH_SBIN2DEC  This function returns the decimal equivalent, both a
% signed and an unsigned version, of the signed binary NxM array of
% numbers passed in.
%
% Parameters: 
% sbin = the array of signed binary values
%
% Author: J. Andy Harriman
% Date: March 24, 2006
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

numBits = length(sbin(1,:));

if(numBits <=1),
    disp('Error: The number of bits must be greater than or equal to 1.')
    result = NaN;
    return
end


k = 1;
for j = 1:1:size(sbin,1),
    signedResult(k) = 0;

    if(sbin(j,1)), %MSB is set
        signedResult(k) = 0-2^(numBits);
    end

    for i = 1:1:numBits,
        signedResult(k) = signedResult(k) + sbin(j,i) * 2^(numBits-i);
    end

    k = k + 1;
end

for j = 1:1:size(sbin,1), %invert the MSB
    if(sbin(j,1)),
        sbin(j,1) = 0;
    else
        sbin(j,1) = 1;
    end
end

k = 1;
for j = 1:1:size(sbin,1),
    unsignedResult(k) = 0;

    for i = 1:1:numBits,
        unsignedResult(k) = unsignedResult(k) + sbin(j,i) * 2^(numBits-i);
    end

    k = k + 1;
end
\end{verbatim}
\normalsize

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\chapter{Design Source Code} \label{appendix:DesignCode}

Due to the fact that the baseband design is primarily composed of \alteraRegPL proprietary megacore functions, and not code developed by the author, the final system design files are included in the enclosed CD-ROM. However, the code for the PN generator module is provided below.

\section{PN Generators}

\scriptsize
\begin{verbatim}
/*************************************************************
*
* This module implements a 10 register PN Generator Circuit.
* 
* Author: J. Andy Harriman
* Date: June 26, 2006
*
**************************************************************/

module PNGenerator(clk, enable, reset, taps, dout);

input clk;
input enable;
input reset;
input [9:1] taps;
output dout;

reg dout;
reg [9:0] temp;
reg [9:0] state;

always @(posedge clk or posedge reset)
begin
	if(reset)
	begin
		dout = 1'b0;
		state = 10'b0000000001;
		//dout = state[0];
	end
	else if(enable)
	begin
		dout = state[0];
		temp = state;
		state[8:0] = temp[9:1];
		state[9] = temp[0]^(taps[1]&temp[1])^(taps[2]&temp[2])^(taps[3]&temp[3])^(taps[4]&temp[4])^
		(taps[5]&temp[5])^(taps[6]&temp[6])^(taps[7]&temp[7])^(taps[8]&temp[8])^(taps[9]&temp[9]);
		//dout = state[0];		
	end
end
endmodule
\end{verbatim}
\normalsize
\newpage

\scriptsize
\begin{verbatim}
/*************************************************************
*
* This module outputs eight different tap configurations for
* the PN Generator. Each of the tap configurations produces
* a maximal length sequenc of 1023 bits.
* 
* Author: J. Andy Harriman
* Date: June 26, 2006
*
**************************************************************/

module TapConfigs(taps1,taps2,taps3,taps4,taps5,taps6,taps7,taps8);

output [9:1] taps1,taps2,taps3,taps4,taps5,taps6,taps7,taps8;

/*
10-bit LRS tap positions... (this is not an exhaustive list)

1. (10,3,0)
2. (10,4,3,1,0)
3. (10,5,2,1,0)
4. (10,5,3,2,0)
5. (10,6,5,2,0)
6. (10,6,5,3,2,1,0)
7. (10,7,0)
8. (10,7,3,1,0)

The PNGenerator block assumes that 10 and 0 are already set (requirement for LRS generator circuit).
Therefore, this block specifies only tap positions 9 through 1 for each configuration.
*/

assign taps1 = 9'b000000100;
assign taps2 = 9'b000001101;
assign taps3 = 9'b000010011;
assign taps4 = 9'b000010110;
assign taps5 = 9'b000110010;
assign taps6 = 9'b000110111;
assign taps7 = 9'b001000000;
assign taps8 = 9'b001000101;

endmodule
\end{verbatim}
\normalsize

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\chapter{Custom PCB Board Designs} \label{appendix:BoardDesigns}

This section provides the schematics, board layouts, and simulation results for the various PCB boards developed for this thesis.

\section{FPGA to Hittite Signal Conditioning Circuit}

Figures \ref{fig:SigCondCircuitSchemticPage1} and \ref{fig:SigCondCircuitSchemticPage2} show the schematic for the board, while \autoref{fig:SigCondCircuitLayout} illustrates the PCB board layout, and \autoref{fig:SigCondCircuitSimulation} provides the \pspiceReg simulation results for the circuit design.

\begin{figure}[!htbp] 
\begin{center}
%\rotatebox{90}{\scalebox{0.8}{\includegraphics{./figures/SigCondCircuitSchematic}}}
\rotatebox{90}{\scalebox{0.9}{\includegraphics[width=\textheight,keepaspectratio]{./figures/SigCondCircuitSchematic_page1}}}
\caption{Hittite Signal Conditioning Circuit Schematic, Page 1/2} \label{fig:SigCondCircuitSchemticPage1}
\end{center}
\end{figure}

\begin{figure}[!htbp] 
\begin{center}
%\rotatebox{90}{\scalebox{0.8}{\includegraphics{./figures/SigCondCircuitSchematic}}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/SigCondCircuitSchematic_page2}
\caption{Hittite Signal Conditioning Circuit Schematic, Page 2/2} \label{fig:SigCondCircuitSchemticPage2}
\end{center}
\end{figure}

\begin{figure}[!htbp] 
\begin{center}
%\scalebox{0.45}{\includegraphics{./figures/SigCondCircuitLayout}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/SigCondCircuitLayout}
\caption{Hittite Signal Conditioning Circuit PCB Layout} \label{fig:SigCondCircuitLayout}
\end{center}
\end{figure}

\begin{figure}[!htbp] 
\begin{center}
%\rotatebox{90}{\scalebox{0.8}{\includegraphics{./figures/SigCondCircuitSimulation}}}
\rotatebox{90}{\includegraphics[height=\textwidth,keepaspectratio]{./figures/SigCondCircuitSimulation}}
\caption{Hittite Signal Conditioning Circuit Simulation} \label{fig:SigCondCircuitSimulation}
\end{center}
\end{figure}

\section{Hittite Bias Circuit}

\autoref{fig:HittiteBiasCircuitSchematic} provides the schematic for the Hittite bias circuit design.

\begin{figure}[!htbp] 
\begin{center}
%\scalebox{0.7}{\includegraphics{./figures/HittiteBiasCircuit}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/HittiteBiasCircuit}
\caption{Hittite Bias Circuit Schematic} \label{fig:HittiteBiasCircuitSchematic}
\end{center}
\end{figure}

\section{Clock Signal Level Translator}

\autoref{fig:ClockLevelTranslatorSchematic} illustrates the circuit schematic for the clock signal level translator board design. The PCB board layout for this design is shown in \autoref{fig:ClockLevelTranslatorLayout}.

\begin{figure}[!htbp] 
\begin{center}
%\scalebox{0.5}{\includegraphics{./figures/ComparatorSchematic}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/ComparatorSchematic}
\caption{Clock Level Translator Circuit Schematic} \label{fig:ClockLevelTranslatorSchematic}
\end{center}
\end{figure}

\begin{figure}[!htbp] 
\begin{center}
%\scalebox{0.5}{\includegraphics{./figures/ComparatorLayout}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/ComparatorLayout}
\caption{Clock Level Translator Circuit Layout} \label{fig:ClockLevelTranslatorLayout}
\end{center}
\end{figure}

\section{GPIO-to-SMA Testpoint Board}

This board was created for use as a debugging tool. It provides eight SMA testpoint connections to user programmable GPIO pins in the FPGA. The schmatic and layout for this PCB board can be found in Figures \ref{fig:TestpointBoardSchematic} and \ref{fig:TestpointBoardLayout} respectively.
\\ %insert a vertical space before the image
\begin{figure}[!htbp] 
\begin{center}
%\scalebox{0.15}{\includegraphics{./figures/TestpointSchematic}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/TestpointSchematic}
\caption{GPIO-to-SMA Testpoint Board Schematic} \label{fig:TestpointBoardSchematic}
\end{center}
\end{figure}

\begin{figure}[!htbp] 
\begin{center}
%\scalebox{0.5}{\includegraphics{./figures/TestpointLayout}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/TestpointLayout}
\caption{GPIO-to-SMA Testpoint Board Layout} \label{fig:TestpointBoardLayout}
\end{center}
\end{figure}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\chapter{Modifications to the Power Supply} \label{appendix:PowerSupplyMods}

In order to make use of a PC power supply for general purpose applications, a dummy load must be applied in order for the supply to switch on. For the purposes of this thesis, additional features such as a power switch and status LED were added, but are not strictly required. \autoref{tbl:PowerSupplyWiring} lists the internal wiring of most modern power supplies. This information is generally provided on the label of the power supply.
\\ %insert a vertical space before the table
\begin{table}[!htbp]
\begin{center}
\caption{Power Supply Wiring} \label{tbl:PowerSupplyWiring}
\begin{tabular}{|c|c|}
\hline
%\multicolumn{2}{|c|}{Generating Polynomials}\\
%\hline
Wire Colour& Purpose\\
\hline
\hline
White& -5 V\\
\hline
Red& +5 V\\
\hline
Black& 0 V\\
\hline
Yellow& +12 V\\
\hline
Blue& -12 V\\
\hline
Brown& Sense\\
\hline
Orange& +3.3 V\\
\hline
Purple& +5V Standby\\
\hline
Grey& Power is on\\
\hline
Green& Turn DC on\\
\hline
\end{tabular}
\end{center}
\end{table}

\autoref{fig:PowerSupplyMods} illustrates the wiring changes required to create the power supply used for this thesis. Note that the +5~V standby line is disconnected, and that the appropriate power lines were connected to their corresponding banana connectors.

\begin{figure}[!htbp]
\begin{center}
%\scalebox{0.75}{\includegraphics{./figures/PowerSupplyMods}}
\includegraphics[width=\textwidth,keepaspectratio]{./figures/PowerSupplyMods}
\caption{Power Supply Wiring Modifications} \label{fig:PowerSupplyMods}
\end{center}
\end{figure}
