B. A. White, B. R. Petersen, D. J. Salomon and M. I. Elmasry, "SPIL: A silicon compiler with performance evaluation," in Proc. of ICCAD-86, (Santa Clara, CA, USA), pp. 500-503, Nov. 10-13, 1986.


A silicon compiler is a computer program that generates IC layouts from a high-level specification. The SPIL silicon compiler is a prototype numerical processor design-automation tool developed at the University of Waterloo. A digital signal processing algorithm is specified in a language similar to Pascal, and IC layouts are generated using a simple register-transfer architecture with a data path controlled by a finite-state machine. For a silicon compiler to be an effective design automation tool, it is essential to include some type of performance evaluation to estimate area, speed and power dissipation of the generated chip layout. A design aid called EPAD was developed for performance estimation of propagation delays, power dissipation and silicon area of CMOS VLSI circuits. The objective is to provide the user with an analysis of the IC layouts and to provide SPIL with feedback analysis to be used in performing higher levels of compilation. To improve and evaluate the effectiveness of the compiler and the performance evaluation feature, two design examples were used. The first example was the design of a chip which controls timing and exponent calculation for floating-point addtion and subtraction. The second was for a chip which performs a conversion from adaptive delta modulation to pulse code modulation.

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