A silicon compiler is a computer program that generates IC layouts from a high-level specification. In the SPIL silicon compiler a digital signal processing algorithm is specified in a language similar to Pascal, and IC layouts are generated using a simple register-transfer architecture with a data path controlled by a finite state machine. For a silicon compiler to be an effective design automation tool it is essential to include some type of performance evaluation to estimate power dissipation, layout area and propagation delays of the generated chip layout.
A design aid called EPAD is used for performance estimation of propagation delays, power dissipation and silicon areas of CMOS VLSI circuits. The objective is to provide the designer with an analysis of the IC layout. The designer can use this analysis to change the algorithm or intermediate levels of silicon compilation.
SPIL and EPAD are used in the design of a chip which compresses and decompresses speech by performing conversions between pulse code modulation and adaptive delta modulation. The algorithms for these conversions were written in the SPIL language, and layouts were generated and combined into one coder-decoder (codec) chip. An EPAD analysis was performed on this chip. Simulation files obtained from EPAD made it possible to identify possible design errors and to predict the maximum operating frequency. This was followed by fabrication and testing of the chip. Test results on fabricated chips compare favourably to EPAD predictions. The results made it possible to evaluate the effectiveness of the silicon compiler and to calibrate the performance evaluator.
The goal of this research is to show that the state of the art is advanced enough that a chip can be efficiently designed using SPIL with EPAD and that the chip can satisfy the requirements of specific applications.PDF file, 896 kBytes